公开(公告)号：US20220272012A1

公开(公告)日：2022-08-25

申请号：US17744034

申请日：2022-05-13

Applicant: Intel Corporation

Inventor： S M Iftekharul ALAM ,  Ned SMITH ,  Vesh Raj SHARMA BANJADE ,  Satish C. JHA ,  Christian MACIOCCO ,  Mona VIJ ,  Kshitij A. DOSHI ,  Srikathyayani SRIKANTESWARA ,  Francesc GUIM BERNAT ,  Maruti GUPTA HYDE ,  Alexander BACHMUTSKY

IPC: H04L43/0811 ,  H04L43/0882 ,  H04L43/091 ,  H04L43/062

Abstract: Examples described herein relate to dynamically composing an application as a monolithic implementation or two or more microservices based on telemetry data. In some examples, based on composition of an application as two or more microservices, at least one connection between microservices based on telemetry data is adjusted. In some examples, a switch can be configured to perform forwarding of communications between microservices based on the adjusted at least one connection between microservices.

公开(公告)号：US20230409699A1

公开(公告)日：2023-12-21

申请号：US17948829

申请日：2022-09-20

Applicant: Intel Corporation

Inventor： Scott CONSTABLE ,  Ilya ALEXANDROVICH ,  Ittai ANATI ,  Simon JOHNSON ,  Vincent SCARLATA ,  Mona VIJ ,  Yuan XIAO ,  Bin XING ,  Krystof SMUDZINSKI

IPC: G06F21/53

CPC classification number: G06F21/53 ,  G06F2221/034

Abstract: Detailed herein are examples of determining when to allow access to a trusted execution environment (TEE). For example, using TEE logic associated with software to at least in part: determine that a TEE feature is supported based at least on a value of a bit position in a data structure; and not allow a TEE entry instruction to access to a TEE when the bit position of the data structure is reserved.

公开(公告)号：US20250036751A1

公开(公告)日：2025-01-30

申请号：US18375391

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bin XING ,  Mona VIJ ,  Rajesh POORNACHANDRAN ,  Barry HUNTLEY ,  Scott CONSTABLE ,  Yuan XIAO ,  Xiang CHENG

IPC: G06F21/54 ,  G06F9/30 ,  G06F21/55

Abstract: In one embodiment, an apparatus comprises a cache to store a plurality of instructions and data associated with a trusted execution environment; instruction processing circuitry to execute the plurality of instructions and process the data, the plurality of instructions including one or more instructions with memory operands, wherein responsive to an interrupt or an exception, the instruction processing circuitry is to pause processing the plurality of instructions and execute a handler; and decode circuitry to partially decode a next instruction of the plurality of instructions to be processed following execution of the handler to determine if the next instruction indicates a memory access and, if so, to calculate at least one corresponding memory address, wherein the partial decode is performed in accordance with one or more constant time programming restrictions.

公开(公告)号：US20200004552A1

公开(公告)日：2020-01-02

申请号：US16024733

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Fangfei LIU ,  Bin XING ,  Michael STEINER ,  Mona VIJ ,  Carlos ROZAS ,  Francis MCKEEN ,  Meltem OZSOY ,  Matthew FERNANDEZ ,  Krystof ZMUDZINSKI ,  Mark SHANAHAN

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

Abstract: Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.

公开(公告)号：US20190332427A1

公开(公告)日：2019-10-31

申请号：US16474905

申请日：2017-04-21

Applicant: INTEL CORPORATION

Inventor： Hongliang TIAN ,  Shoumeng YAN ,  Mona VIJ

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/32

Abstract: Preemptive scheduling enclaves as disclosed herein support both cooperative and preemptive scheduling of in-enclave (IE) thread execution. These preemptive scheduling enclaves may include a scheduler configured to be executed as part of normal hardware interrupt processing by enclave threads. The scheduler identifies an IE thread to be scheduled and modifies enclave data structures so that when the enclave thread resumes processing after a hardware interrupt, the identified IE thread is executed, rather than the interrupted IE thread.