公开(公告)号：US20230409699A1

公开(公告)日：2023-12-21

申请号：US17948829

申请日：2022-09-20

Applicant: Intel Corporation

Inventor： Scott CONSTABLE ,  Ilya ALEXANDROVICH ,  Ittai ANATI ,  Simon JOHNSON ,  Vincent SCARLATA ,  Mona VIJ ,  Yuan XIAO ,  Bin XING ,  Krystof SMUDZINSKI

IPC: G06F21/53

CPC classification number: G06F21/53 ,  G06F2221/034

Abstract: Detailed herein are examples of determining when to allow access to a trusted execution environment (TEE). For example, using TEE logic associated with software to at least in part: determine that a TEE feature is supported based at least on a value of a bit position in a data structure; and not allow a TEE entry instruction to access to a TEE when the bit position of the data structure is reserved.

公开(公告)号：US20240427636A1

公开(公告)日：2024-12-26

申请号：US18213189

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Fangfei LIU ,  Carlos ROZAS ,  Thomas UNTERLUGGAUER ,  Scott CONSTABLE

IPC: G06F9/50

Abstract: An apparatus and method for securely reserving resources for trusted execution. For example, one embodiment of a processor comprises: a plurality of cores, each core of the plurality of cores to provide at least one logical processor of a plurality of logical processors; a first plurality of registers, each register of the first plurality of registers to associate a class of service (CLOS) value with a corresponding logical processor of the plurality of logical processors; a second plurality of registers, each register of the second plurality of registers to indicate a portion of a shared resource to be allocated to a corresponding CLOS value; a first control register of a first logical processor of the plurality of logical processors to be configured with a reserved CLOS value associated with a trusted control structure; resource reservation circuitry configurable by secure firmware or software to indicate a reserved portion of the shared resource associated with the reserved CLOS value; and enforcement circuitry to limit access to the reserved portion of the shared resource to threads or logical processors associated with the reserved CLOS value.

公开(公告)号：US20250036751A1

公开(公告)日：2025-01-30

申请号：US18375391

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bin XING ,  Mona VIJ ,  Rajesh POORNACHANDRAN ,  Barry HUNTLEY ,  Scott CONSTABLE ,  Yuan XIAO ,  Xiang CHENG

IPC: G06F21/54 ,  G06F9/30 ,  G06F21/55

Abstract: In one embodiment, an apparatus comprises a cache to store a plurality of instructions and data associated with a trusted execution environment; instruction processing circuitry to execute the plurality of instructions and process the data, the plurality of instructions including one or more instructions with memory operands, wherein responsive to an interrupt or an exception, the instruction processing circuitry is to pause processing the plurality of instructions and execute a handler; and decode circuitry to partially decode a next instruction of the plurality of instructions to be processed following execution of the handler to determine if the next instruction indicates a memory access and, if so, to calculate at least one corresponding memory address, wherein the partial decode is performed in accordance with one or more constant time programming restrictions.