公开(公告)号：US20230098467A1

公开(公告)日：2023-03-30

申请号：US17485176

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Patrick THEOFANIS ,  Charles MOKHTARZADEH ,  Matthew V. METZ ,  Scott B. CLENDENNING

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/66

Abstract: Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.

公开(公告)号：US20230101370A1

公开(公告)日：2023-03-30

申请号：US17485181

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Sudarat LEE ,  Chelsey DOROW ,  Kevin P. O'BRIEN ,  Carl H. NAYLOR ,  Kirby MAXEY ,  Charles MOKHTARZADEH ,  Ashish Verma PENUMATCHA ,  Scott B. CLENDENNING ,  Uygar E. AVCI

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Thin film transistors having multi-layer gate dielectric structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a two-dimensional (2D) material layer above a substrate. A gate stack is over the 2D material layer, the gate stack having a first side opposite a second side, and the gate stack having a gate electrode around a gate dielectric structure. A first gate spacer is on the 2D material layer and adjacent to the first side of the gate stack. A second gate spacer is on the 2D material layer and adjacent to the second side of the gate stack, wherein the first gate spacer and the second gate spacer are continuous with a layer of the gate dielectric structure. A first conductive structure is coupled to the 2D material layer and adjacent to the first gate spacer. A second conductive structure is coupled to the 2D material layer and adjacent to the second gate spacer.