公开(公告)号：US20190221577A1

公开(公告)日：2019-07-18

申请号：US16324479

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Patrick THEOFANIS ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Stephen M. CEA

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11575

Abstract: An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polyconductive material.

公开(公告)号：US20230098467A1

公开(公告)日：2023-03-30

申请号：US17485176

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Shriram SHIVARAMAN ,  Uygar E. AVCI ,  Patrick THEOFANIS ,  Charles MOKHTARZADEH ,  Matthew V. METZ ,  Scott B. CLENDENNING

IPC: H01L27/092 ,  H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8256 ,  H01L29/66

Abstract: Thin film transistors having a spin-on two-dimensional (2D) channel material are described. In an example, an integrated circuit structure includes a first device layer including a first two-dimensional (2D) material layer above a substrate. The first 2D material layer includes molybdenum, sulfur, sodium and carbon. A second device layer including a second 2D material layer is above the substrate. The second 2D material layer includes tungsten, selenium, sodium and carbon.

公开(公告)号：US20170158501A1

公开(公告)日：2017-06-08

申请号：US15301337

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Jorge A. MUNOZ ,  Dmitri E. NIKONOV ,  Kelin J. KUHN ,  Patrick THEOFANIS ,  Chytra PAWASHE ,  Kevin LIN ,  Seiyon KIM

IPC: B82B1/00 ,  H01H59/00 ,  B82B3/00 ,  H01L29/66 ,  H01L29/84 ,  H01L29/82

CPC classification number: B82B1/005 ,  B81B3/0016 ,  B81B7/02 ,  B81B2201/014 ,  B81B2203/0118 ,  B82B1/002 ,  B82B3/0023 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01H1/0094 ,  H01H1/54 ,  H01H59/0009 ,  H01L29/66227 ,  H01L29/82 ,  H01L29/84 ,  Y10S977/732 ,  Y10S977/838 ,  Y10S977/888 ,  Y10S977/938

Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.