公开(公告)号：US09893746B2

公开(公告)日：2018-02-13

申请号：US14749766

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Shu-Ping Yeh ,  Feng Xue ,  Anuja Surendra Vaidya

IPC: H04B3/20 ,  H04B1/04 ,  H04B1/12 ,  H04L5/14 ,  H04B1/525

CPC classification number: H04B1/0475 ,  H04B1/12 ,  H04B1/525 ,  H04L5/14

Abstract: A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.

公开(公告)号：US20170085252A1

公开(公告)日：2017-03-23

申请号：US14861421

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Feng Xue ,  Anuja S. Vaidya ,  Eduardo X. Alban ,  Albert Oskar Filip Andersson ,  Chia-Hsiang Chen ,  Shu-Ping Yeh

IPC: H03H21/00 ,  G06F17/16

CPC classification number: H03H21/0012 ,  G06F9/3877 ,  G06F17/16 ,  H03H2021/0049 ,  H03H2021/0094 ,  H03H2218/06 ,  H04B1/525

Abstract: An adaptation hardware accelerator comprises a calculation unit configured to receive a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determine a correlation data and a cross-correlation data based thereon for a given calculation iteration. The correlation data comprises a correlation matrix comprising a plurality of sub-matrices, wherein determining the correlation matrix comprises determining only the submatrices in an upper triangular portion and a diagonal portion of the correlation matrix. Further, the adaptation hardware accelerator comprises an adaptation core unit configured to determine a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, based on an optimized RLS based adaptive algorithm, by utilizing the correlation data and the cross correlation data. In addition, the hardware accelerator unit comprises a convergence detector unit configured to determine a convergence parameter; and a controller configured to generate an iteration signal for each of the predefined time intervals based on the convergence parameter. The iteration signal communicates to the calculation unit and the adaptation core unit to continue with a next calculation iteration or to conclude, wherein the conclusion indicates a determination of a final value of the plurality of the adaptive weights by the adaptation core unit.

公开(公告)号：US10193683B2

公开(公告)日：2019-01-29

申请号：US15214531

申请日：2016-07-20

Applicant: Intel Corporation

Inventor： Chia-Hsiang Chen ,  Ching-En Lee ,  Feng Xue ,  Shu-Ping Yeh

IPC: H04L5/14 ,  H04B1/44 ,  H04B15/00 ,  H04B1/525

Abstract: A communication circuit arrangement includes a signal path circuit configured to separately apply a kernel dimension filter and a delay tap dimension filter to an input signal for an amplifier to obtain an estimated interference signal, a cancelation circuit configured to subtract the estimated interference signal from a received signal to obtain a clean signal, and a filter update circuit configured to alternate between updating the kernel dimension filter and the delay tap dimension filter using the clean signal.

公开(公告)号：US09935615B2

公开(公告)日：2018-04-03

申请号：US14861421

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Feng Xue ,  Anuja S. Vaidya ,  Eduardo X. Alban ,  Albert Oskar Filip Andersson ,  Chia-Hsiang Chen ,  Shu-Ping Yeh

IPC: G06F17/10 ,  H03H21/00 ,  G06F17/16 ,  G06F9/38 ,  H04B1/525

CPC classification number: H03H21/0012 ,  G06F9/3877 ,  G06F17/16 ,  H03H2021/0049 ,  H03H2021/0094 ,  H03H2218/06 ,  H04B1/525

Abstract: An adaptation hardware accelerator comprises a calculation unit to receive inputs at predefined time interval(s) that correspond to a calculation iteration, the inputs associated with adaptive filters having taps, and determine correlation and cross-correlation data based thereon for a given iteration. The correlation data comprises a correlation matrix. Determining the matrix comprises determining submatrices in an upper triangular portion and a diagonal portion of the matrix. The accelerator comprises an adaptation core unit to determine adaptive weights associated with the adaptive filters, respectively, based on an adaptive algorithm, utilizing the correlation and cross correlation data. The accelerator unit comprises a convergence detector unit to determine a convergence parameter; and a controller to generate an iteration signal for each time interval based on the parameter. The iteration signal communicates to continue or conclude; the conclusion indicates determination of a final value of adaptive weights by the core unit.

公开(公告)号：US20160380653A1

公开(公告)日：2016-12-29

申请号：US14749766

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Shu-Ping Yeh ,  Feng Xue ,  Anuja Surendra Vaidya

IPC: H04B1/04 ,  H04L5/14 ,  H04B1/12

CPC classification number: H04B1/0475 ,  H04B1/12 ,  H04B1/525 ,  H04L5/14

Abstract: A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.

Abstract translation: 多项式核心生成器被配置为从包括通信设备或系统中的非线性分量的发射机路径减轻接收机路径中的非线性。 多项式核心发生器用于产生可用于将非线性建模为应用于非线性的非线性函数的分段多项式逼近的函数的多项式内核。 多项式内核生成器使用固定数量的加法器在日志域中使用多项式计算，在乘数少的架构中生成内核。