公开(公告)号：US12166480B2

公开(公告)日：2024-12-10

申请号：US17346034

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Chinmay Joshi ,  Dinesh Somasekhar

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/0185 ,  H03K19/173 ,  H03K19/21

Abstract: A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.

公开(公告)号：US20220399893A1

公开(公告)日：2022-12-15

申请号：US17346034

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Chinmay Joshi ,  Dinesh Somasekhar

IPC: H03K19/0185 ,  H03K19/173 ,  H03K19/21 ,  H03K3/3562

Abstract: A single-phase clocked data multiplexer (MUX-D) scan capable flipflop (FF) design that improves over existing transmission-gate (t-gate) based master-slave flipflops in terms of dynamic capacitance (Cdyn) as well as performance while remaining comparable in area. Unique features of the design are a complementary metal oxide semiconductor (non-t-gate) style structure with an improvement in circuit parameters achieved by eliminating clock inversions and maximally sharing NMOS devices across NAND structures. The core of the flipflop adopts an all CMOS NAND, And-OR-Inverter (AOI) complex logic structure to implement a true edge-triggered flip-flop functionality.