公开(公告)号：US10110225B1

公开(公告)日：2018-10-23

申请号：US15341423

申请日：2016-11-02

Applicant: Intel Corporation

Inventor： Ker Yon Lau ,  Tat Hin Tan ,  Choong Kit Wong

IPC: H03K19/00 ,  H03K17/56

Abstract: An input/output (I/O) circuit for an integrated circuit includes an input-output terminal, a termination circuit and an impedance compensation circuit. The termination circuit includes a node that is coupled to the input-output terminal. The termination circuit exhibits substantially constant first impedance below a first frequency of signals received at the input-output terminal. Furthermore, the termination circuit exhibits second impedance that is less than the first impedance when signals having a second frequency that is higher than the first frequency are received at the input-output terminal. The impedance compensation circuit is coupled to the input-output terminal. The impedance compensation circuit compensates for differences between the first and second impendences when the signal having the second frequency that is higher than the first frequency is received at the input-output terminal.