公开(公告)号：US20240429235A1

公开(公告)日：2024-12-26

申请号：US18337697

申请日：2023-06-20

Applicant: Intel Corporation

Inventor： Bilal Chehab ,  Changyok Park ,  Tuhin Guha Neogi ,  George Joseph Sacks ,  Christophe Berteau-Pavy

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/778 ,  H01L29/786

Abstract: A CFET may include two or more transistors stacked over each other. A transistor may be a FET including a forked semiconductor structure. The source region and drain region of a transistor may have a forked shape including a body and one or more branches protruding from the body. A branch may include a fin, nanoribbon, etc. The channel region may be between a branch of the source region and a branch of the drain region. The body of the source region and the body of the drain region may be on opposite sides of the channel region in two perpendicular directions. The two bodies may be diagonally arranged with respect to the channel region. The body of the source region or drain region may be over a contact that is electrically coupled to a frontside metal layer or a backside metal layer for signal transmission or power delivery.