公开(公告)号：US12009023B2

公开(公告)日：2024-06-11

申请号：US17441667

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Zhenglong Wu ,  Tonia G. Morris ,  Christina Jue ,  Daniel Becerra Perez ,  David G. Ellis

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: A reference voltage value and a chip select (CS) signal timing delay provided to memory devices can be determined based on samples of the CS signal received by the memory devices. The CS signal can be provided to the memory devices with varying time delays and for various reference voltages. Various samples of the CS signal from the memory devices can indicate different times for rising and falling edges of the CS signal. A composite signal eye can be generated by the latest occurring rising edge and the earliest occurring falling edge of the CS signal. The reference voltage value and timing delay can be chosen based on the composite signal eye width that is the closest to a reference eye width.

公开(公告)号：US20180090198A1

公开(公告)日：2018-03-29

申请号：US15274757

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Daniel Becerra Perez

IPC: G11C11/4099 ,  G11C11/4096 ,  G06F3/06

CPC classification number: G11C11/4096 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254

Abstract: A disclosed example includes setting a first reference voltage value in a memory device for use during operation of the memory device in a per-device addressability (PDA) mode, the first reference voltage value for use by the memory device to determine a first logic value at a data line of the memory device during the PDA mode, the PDA mode to enable access to the memory device exclusive of other memory devices in circuit with the memory device; and setting a second reference voltage value in the memory device for use during operation of the memory device in a non-PDA mode, the non-PDA mode to enable writing data to the memory device, the second reference voltage value for use by the memory device to determine a second logic value at the data line of the memory device during a write operation.