公开(公告)号：US20220391668A1

公开(公告)日：2022-12-08

申请号：US17845701

申请日：2022-06-21

Applicant: INTEL CORPORATION

Inventor： Daniel Cummings ,  Maciej Szankin ,  Sharath Nittur Sridhar ,  Anthony Sarah

IPC: G06N3/04 ,  G06N3/08

Abstract: Methods, apparatus, systems, and articles of manufacture to iteratively search for an artificial intelligence-based architecture are disclosed. An example apparatus includes an interface to access a first subgroup of architecture configurations from a search space; instructions; and processor circuitry to execute the instructions to: train first predictors based on the first subgroup; generate a first plurality of candidate architecture configurations using the trained first predictors; and generate a second subgroup of architecture configurations by selecting a number of the plurality of candidate architecture configurations; train second predictors based on the first subgroup and the second subgroup; and generate a second plurality of candidate architecture configurations using the trained second predictors.

公开(公告)号：US12130654B2

公开(公告)日：2024-10-29

申请号：US18092074

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Amir Javidi ,  Daniel Cummings ,  Glenn Starnes

IPC: G06F1/06 ,  G06F1/3206 ,  G11C7/10

CPC classification number: G06F1/06 ,  G06F1/3206 ,  G11C7/1039 ,  G11C7/1075

Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

公开(公告)号：US20220318595A1

公开(公告)日：2022-10-06

申请号：US17848226

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Sharath Nittur Sridhar ,  Daniel Cummings ,  Juan Pablo Munoz ,  Anthony Sarah

IPC: G06N3/04 ,  G06N5/04 ,  G06N5/02

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve neural architecture searches. An example apparatus includes similarity verification circuitry to identify candidate networks based on a combination of a target platform type, a target workload type to be executed by the target platform type, and historical benchmark metrics corresponding to the candidate networks, the candidate networks associated with performance metrics. The example apparatus also includes likelihood verification circuitry to categorize (a) a first set of the candidate networks based on a first one of the performance metrics corresponding to first tier values, and (b) a second set of the candidate networks based on a second one of the performance metrics corresponding to second tier values, and extract first features corresponding to the first set of the candidate networks and extract second features corresponding to the second set of the candidate networks. The example apparatus also includes network analysis circuitry to improve network analysis efficiency by providing the first features and the second features to a network analyzer to identify particular ones of the candidate networks.

公开(公告)号：US11029720B2

公开(公告)日：2021-06-08

申请号：US16386070

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Amir Javidi ,  Daniel Cummings ,  Glenn Starnes

IPC: G06F1/06 ,  G11C7/10 ,  G06F1/3206

Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

公开(公告)号：US20250131048A1

公开(公告)日：2025-04-24

申请号：US19000201

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Anthony Sarah ,  Daniel Cummings ,  Juan Pablo Munoz ,  Tristan Webb

IPC: G06F16/953 ,  G06N5/02

Abstract: The present disclosure is related to framework for automatically and efficiently finding machine learning (ML) architectures that are optimized to one or more specified performance metrics and/or hardware platforms. This framework provides ML architectures that are applicable to specified ML domains and are optimized for specified hardware platforms in significantly less time than could be done manually and in less time than existing ML model searching techniques. Furthermore, a user interface is provided that allows a user to search for different ML architectures based on modified search parameters, such as different hardware platform aspects and/or performance metrics. Other embodiments may be described and/or claimed.

公开(公告)号：US11619963B2

公开(公告)日：2023-04-04

申请号：US17338550

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Amir Javidi ,  Daniel Cummings ,  Glenn Starnes

IPC: G06F1/06 ,  G11C7/10 ,  G06F1/3206

Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

公开(公告)号：US20220035878A1

公开(公告)日：2022-02-03

申请号：US17505568

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： Anthony Sarah ,  Daniel Cummings ,  Juan Pablo Munoz ,  Tristan Webb

IPC: G06F16/953

Abstract: The present disclosure is related to framework for automatically and efficiently finding machine learning (ML) architectures that are optimized to one or more specified performance metrics and/or hardware platforms. This framework provides ML architectures that are applicable to specified ML domains and are optimized for specified hardware platforms in significantly less time than could be done manually and in less time than existing ML model searching techniques. Furthermore, a user interface is provided that allows a user to search for different ML architectures based on modified search parameters, such as different hardware platform aspects and/or performance metrics. Other embodiments may be described and/or claimed.

公开(公告)号：US20220335286A1

公开(公告)日：2022-10-20

申请号：US17853608

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Daniel Cummings ,  Somdeb Majumdar ,  Anthony Sarah

IPC: G06N3/063 ,  G06N3/04 ,  G06F11/34

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for designing hardware. An example apparatus includes processor circuitry to execute machine readable instructions to determine a first hardware architectural configuration of a hardware component based on a design constraint, simulate an execution of the first hardware architectural configuration for a plurality of workloads to generate a respective plurality of objective design spaces, the objective design spaces based on one or more objectives; generate an aggregate score by aggregating a plurality of design space performance indicators, ones of the plurality of design space performance indicators corresponding to respective ones of the plurality of objective design spaces; search a design database based on the aggregate score to identify a second hardware architectural configuration, and predict a performance of the second hardware architectural configuration to generate a performance metric by executing a proxy function corresponding to the second hardware architectural configuration.