公开(公告)号：US12130654B2

公开(公告)日：2024-10-29

申请号：US18092074

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Amir Javidi ,  Daniel Cummings ,  Glenn Starnes

IPC: G06F1/06 ,  G06F1/3206 ,  G11C7/10

CPC classification number: G06F1/06 ,  G06F1/3206 ,  G11C7/1039 ,  G11C7/1075

Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

公开(公告)号：US11619963B2

公开(公告)日：2023-04-04

申请号：US17338550

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Amir Javidi ,  Daniel Cummings ,  Glenn Starnes

IPC: G06F1/06 ,  G11C7/10 ,  G06F1/3206

Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

公开(公告)号：US11029720B2

公开(公告)日：2021-06-08

申请号：US16386070

申请日：2019-04-16

Applicant: Intel Corporation

Inventor： Amir Javidi ,  Daniel Cummings ,  Glenn Starnes

IPC: G06F1/06 ,  G11C7/10 ,  G06F1/3206

Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.