公开(公告)号：US20240256283A1

公开(公告)日：2024-08-01

申请号：US18566068

申请日：2022-03-31

申请人： Intel Corporation

发明人： Joshua B. Fryman ,  Byoungchan Oh ,  Sai Dheeraj Polagani ,  Kevin P. Ma ,  Robert S. Pawlowski ,  Bharadwaj Coimbatore Krishnamurthy ,  Shruti Sharma ,  Smitha P. Vasantha Kumar ,  Jason Howard ,  Daniel S. Klowden

IPC分类号： G06F9/38 ,  G06F11/34

CPC分类号： G06F9/3851 ,  G06F11/3409

摘要： A system is provided that includes a set of graph processing cores and a set of dense compute cores. where the set of graph processing cores and the set of dense cores are interconnected in a network. The dense compute cores include offload queue circuitry to receive an offload request from the set of graph processing cores to handle dense compute workloads. Memory controllers are also provided in the system for use by the graph processing cores in reading and writing to memory in association with sparse graph applications. the memory controllers enhanced to efficiently handle memory transactions in sparse graph applications.