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公开(公告)号:US12158625B2
公开(公告)日:2024-12-03
申请号:US17132967
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Kaveh Hosseini , Xiaoqian Li , Conor O'Keeffe , Jing Fang , Kevin P. Ma , Shamsul Abedin
Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a bidirectional optical grating coupler that may be used for testing. A photonic apparatus includes a first layer with electro-optical circuitry that is optically coupled with a bidirectional optical grating coupler. A second layer is physically coupled with a first side of the first layer and includes a first light path to optically coupled with the bidirectional optical grating coupler. A third layer is physically coupled with a second side of the first layer opposite the first side of the first layer, and includes a second light path that optically couples with the bidirectional grating coupler. Operational testing of the electro-optical circuitry is based in part on light received or transmitted through the second light path. Other embodiments may be described and/or claimed.
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公开(公告)号:US20240256283A1
公开(公告)日:2024-08-01
申请号:US18566068
申请日:2022-03-31
Applicant: Intel Corporation
Inventor: Joshua B. Fryman , Byoungchan Oh , Sai Dheeraj Polagani , Kevin P. Ma , Robert S. Pawlowski , Bharadwaj Coimbatore Krishnamurthy , Shruti Sharma , Smitha P. Vasantha Kumar , Jason Howard , Daniel S. Klowden
CPC classification number: G06F9/3851 , G06F11/3409
Abstract: A system is provided that includes a set of graph processing cores and a set of dense compute cores. where the set of graph processing cores and the set of dense cores are interconnected in a network. The dense compute cores include offload queue circuitry to receive an offload request from the set of graph processing cores to handle dense compute workloads. Memory controllers are also provided in the system for use by the graph processing cores in reading and writing to memory in association with sparse graph applications. the memory controllers enhanced to efficiently handle memory transactions in sparse graph applications.
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