公开(公告)号：US11756941B2

公开(公告)日：2023-09-12

申请号：US16379607

申请日：2019-04-09

Applicant: Intel Corporation

Inventor： John Fallin ,  Daniel Willis

IPC: H01L23/50 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42 ,  H01L49/02 ,  H01L23/522 ,  H01G4/30

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/5223 ,  H01L24/17 ,  H01L28/40 ,  H01G4/30 ,  H01L2224/0401 ,  H01L2924/1205

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of dies on a package substrate, and a plurality of smart dies on the package substrate, where the plurality of smart dies include a plurality of interconnects and a plurality of capacitors. The semiconductor package also includes a plurality of routing lines coupled to the dies and the smart dies, where the routing lines are communicatively coupled to the interconnects of the smart dies, where each of the dies has at least two or more routing lines to communicatively couple the dies together, and where one of the routing lines is via the interconnects of the smart dies. The capacitors may be a plurality of metal-insulator-metal (MIM) capacitors. The dies may be a plurality of active dies. The routing lines may communicatively couple first and second active dies to first and second smart dies.

公开(公告)号：US20190042270A1

公开(公告)日：2019-02-07

申请号：US16024151

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Daniel Willis ,  Jonathan Thibado ,  Eugene Nelson

IPC: G06F9/38 ,  G06F9/30

Abstract: The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and to optimize processor performance based on the connection type. As a non-limiting example, a processor package consistent with the present disclosure may include a central processing unit (CPU) die and a plurality of pins (including two connection detection pins) to connect the package to a motherboard. The CPU die may include connection determination logic and execution policy logic, implemented via processor code (“p-code”), as well as a more typical processor.

公开(公告)号：US20190306984A1

公开(公告)日：2019-10-03

申请号：US15941427

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Daniel Willis ,  Dan H. Gerbus

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/46 ,  H01L23/32 ,  H01L23/367

Abstract: The present subject matter may include an electronic device. The electronic device may include a motherboard socket body. The motherboard socket body may be adapted to couple with a processor. The motherboard socket body may define an aperture in the motherboard socket body. The electronic device may include a socket insulator. The socket insulator may be coupled with the aperture in the motherboard socket body. The socket insulator may include an insulator body that may be sized and shaped to close the aperture in the motherboard socket body. The socket insulator may be configured to isolate electrical communication in portions of the motherboard socket body.

公开(公告)号：US10729010B2

公开(公告)日：2020-07-28

申请号：US15941427

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Daniel Willis ,  Dan H. Gerbus

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/46 ,  H01L23/32 ,  H01L23/367

Abstract: The present subject matter may include an electronic device. The electronic device may include a motherboard socket body. The motherboard socket body may be adapted to couple with a processor. The motherboard socket body may define an aperture in the motherboard socket body. The electronic device may include a socket insulator. The socket insulator may be coupled with the aperture in the motherboard socket body. The socket insulator may include an insulator body that may be sized and shaped to close the aperture in the motherboard socket body. The socket insulator may be configured to isolate electrical communication in portions of the motherboard socket body.

公开(公告)号：US11023247B2

公开(公告)日：2021-06-01

申请号：US16024151

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Daniel Willis ,  Jonathan Thibado ,  Eugene Nelson

IPC: G06F9/38 ,  G06F9/30 ,  H01L23/31

Abstract: The systems and methods disclosed herein provide an improved processor package to determine a connection type between the package and an external circuit and to optimize processor performance based on the connection type. As a non-limiting example, a processor package consistent with the present disclosure may include a central processing unit (CPU) die and a plurality of pins (including two connection detection pins) to connect the package to a motherboard. The CPU die may include connection determination logic and execution policy logic, implemented via processor code (“p-code”), as well as a more typical processor.