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公开(公告)号：US11558158B2
公开(公告)日：2023-01-17
申请号：US17093679
申请日：2020-11-10
Applicant: Intel Corporation
Inventor： Michael Shusterman , John Fallin , Ana M. Yepes , Dong-Ho Han , Nasser A. Kurd , Tomer Levy , Ehud Reshef , Arik Gihon , Ido Ouzieli , Yevgeni Sabin , Maor Tal , Zhongsheng Wang , Amit Zeevi
Abstract: A wireless communication device for communicating across a wireless communication channel includes one or more processors configured to determine whether a further device is generating a radio frequency interference at an operating frequency; transmit a request message to the further device requesting the further device vacate the operating frequency based on the determination that the further device is generating radio frequency interference; receive a response message from the further device; and generate an instruction based on the response message.
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公开(公告)号：US11756941B2
公开(公告)日：2023-09-12
申请号：US16379607
申请日：2019-04-09
Applicant: Intel Corporation
Inventor： John Fallin , Daniel Willis
CPC classification number: H01L25/16 , H01L23/3128 , H01L23/42 , H01L23/5223 , H01L24/17 , H01L28/40 , H01G4/30 , H01L2224/0401 , H01L2924/1205
Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of dies on a package substrate, and a plurality of smart dies on the package substrate, where the plurality of smart dies include a plurality of interconnects and a plurality of capacitors. The semiconductor package also includes a plurality of routing lines coupled to the dies and the smart dies, where the routing lines are communicatively coupled to the interconnects of the smart dies, where each of the dies has at least two or more routing lines to communicatively couple the dies together, and where one of the routing lines is via the interconnects of the smart dies. The capacitors may be a plurality of metal-insulator-metal (MIM) capacitors. The dies may be a plurality of active dies. The routing lines may communicatively couple first and second active dies to first and second smart dies.
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Patent Agency Ranking
公开(公告)号：US20200005728A1
公开(公告)日：2020-01-02
申请号：US16019924
申请日：2018-06-27
Applicant: Intel Corporation
Inventor： Nasser Kurd , Daniel Ragland , Ameya Ambardekar , John Fallin , Praveen Mosalikanti , Vaughn J. Grossnickle
Abstract: Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.
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公开(公告)号：US20220209778A1
公开(公告)日：2022-06-30
申请号：US17698844
申请日：2022-03-18
Applicant: Intel Corporation
Inventor： Kuan-Yueh Shen , Nasser A. Kurd , John Fallin
Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
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公开(公告)号：US10796977B2
公开(公告)日：2020-10-06
申请号：US16292218
申请日：2019-03-04
Applicant: Intel Corporation
Inventor： John Fallin , Daniel J. Ragland , Jonathan P. Douglas
IPC: H05K7/00 , H05K7/20 , H01L23/34 , H01L23/367 , H01L23/467 , H01L23/473 , G06F1/20 , G06F1/26 , G06F17/50 , G11C5/00 , G11C29/50 , G06F11/14
Abstract: Circuitry to apply heat to a die while the die junction temperature is below a minimum die junction temperature of an operating die junction temperature range for the die is provided. The circuitry to avoid a system boot failure when the die junction temperature is below the operating die junction temperature range of the die.
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公开(公告)号：US12009827B2
公开(公告)日：2024-06-11
申请号：US17698844
申请日：2022-03-18
Applicant: Intel Corporation
Inventor： Kuan-Yueh Shen , Nasser A. Kurd , John Fallin
CPC classification number: H03L7/0992 , H01R13/665 , H03L7/0893 , H03L7/189 , H01R2201/06
Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
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公开(公告)号：US11309900B2
公开(公告)日：2022-04-19
申请号：US16913933
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Kuan-Yueh Shen , Nasser A. Kurd , John Fallin
Abstract: Some embodiments include apparatuses having a first path in a phase locked loop, the first path including a phase frequency detector to receive a first signal having a first frequency and a first node to provide a voltage; an oscillator coupled to a second node and the first node to provide a second signal having a second frequency at the second node; a second path including a frequency divider coupled to the second node and the phase frequency detector; and a circuit to generate digital information having a value based on a value of the voltage at the second node.
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