公开(公告)号：US20230004389A1

公开(公告)日：2023-01-05

申请号：US17358231

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Joseph Williams ,  Zoran Zivkovic ,  Jian-Guo Chen ,  Hong Wan ,  David Dougherty ,  Jay O'neill

IPC: G06F9/30

Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

公开(公告)号：US12282774B2

公开(公告)日：2025-04-22

申请号：US17358231

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Joseph Williams ,  Zoran Zivkovic ,  Jian-Guo Chen ,  Hong Wan ,  David Dougherty ,  Jay O'neill

IPC: G06F9/30

Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

公开(公告)号：US20240220249A1

公开(公告)日：2024-07-04

申请号：US18147099

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Jian-Guo Chen ,  David Dougherty ,  Madihally Narasimha ,  Joseph Othmer ,  Hong Wan ,  Joseph Williams ,  Zoran Zivkovic

IPC: G06F9/30 ,  G06F30/343

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F30/343

Abstract: Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.