公开(公告)号：US20240134818A1

公开(公告)日：2024-04-25

申请号：US18533369

申请日：2023-12-08

Applicant: Intel Corporation

Inventor： Zoran Zivkovic ,  Jian-Guo Chen ,  Jay ONeill ,  Joseph Williams

IPC: G06F15/80 ,  G06F1/03

CPC classification number: G06F15/8007 ,  G06F1/03

Abstract: Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a look-up table (LUT) in accordance with a fused single instruction stream, multiple data streams (SIMD) instruction. The LUT may contain segment entries that correspond to a result of evaluating a function using a corresponding index values, which represent an independent variable of the function. The index values are used to map data sample values in a data array that is to be interpolated to the segment entries. By using an iterative process of mapping data samples to valid segment entries contained in each LUT portion, the architecture advantageously facilitates scaling to support larger LUTs and thus may be expanded to enable linear interpolation on multiple dimensions.

公开(公告)号：US09184787B2

公开(公告)日：2015-11-10

申请号：US13800167

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Meng-Lin Yu ,  Jian-Guo Chen ,  Alexander Alexandrovich Petyushko ,  Ivan Leonidovich Mazurenko

IPC: H04B1/00 ,  H04B1/709 ,  H04B1/7113

CPC classification number: H04B1/709 ,  H04B1/7113

Abstract: In one embodiment, a programmable vector processor performs preamble detection in a wireless communication network. Implementation of preamble detection in the vector processor is made possible by a set of vector instructions that include (i) a circular load instruction for loading vectors of received data, (ii) a correlation instruction for correlating the vectors of received data with vectors of the scrambling code to concurrently generate a plurality of complex correlations, (iii) a partial-transpose instruction for arranging vectors of the complex correlations for use by a Fast Hadamard Transform (FHT) processor, and (iv) an FHT instruction for performing FHT processing on a vector of complex correlations. Implementing preamble detection in the vector processor allows more of the received data to be processed concurrently. As a result, preamble detectors of the disclosure may detect preambles using fewer clock cycles than that of comparable preamble detectors implemented using hardware accelerators.

Abstract translation: 在一个实施例中，可编程向量处理器在无线通信网络中执行前导码检测。 矢量处理器中的前导码检测的实现可以通过一组向量指令成为可能的，该矢量指令包括（i）用于加载接收数据的向量的循环加载指令，（ii）将接收到的数据的向量与 扰码以同时产生多个复相关，（iii）用于排列复数相关的向量的部分转置指令，供快速哈达马变换（FHT）处理器使用，以及（iv）用于对FHT处理执行FHT处理的FHT指令 复杂相关的向量。 在矢量处理器中实现前同步码检测允许更多的接收数据被同时处理。 结果，本公开的前导码检测器可以使用比使用硬件加速器实现的可比较的前同步码检测器更少的时钟周期来检测前导码。

公开(公告)号：US11334356B2

公开(公告)日：2022-05-17

申请号：US16457994

申请日：2019-06-29

Applicant: Intel Corporation

Inventor： Jian-Guo Chen ,  David T. Dougherty ,  Steven Pinault ,  Parakalan Venkataraghavan ,  Joseph Williams ,  Meng-Lin Yu ,  Kamran Azadet

IPC: G06F9/30 ,  H04L49/25 ,  H04L49/201 ,  G06F9/54

Abstract: Systems, methods, and apparatuses relating to a user defined formatting instruction to configure multicast Benes network circuitry are described. In one embodiment, a processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having fields that identify packed input data, packed control data, and a packed data destination; and an execution unit to execute the decoded single instruction to: send the packed control data to respective control inputs of a circuit that comprises an inverse butterfly circuit coupled in series to a butterfly circuit, wherein the inverse butterfly circuit comprises a first plurality of stages of multicast switches and the butterfly circuit comprises a second plurality of stages of multicast switches, read, once from storage separate from the circuit, each element of the packed input data as respective inputs of the circuit, route the packed input data through the circuit according to the packed control data, and store resultant packed data from the circuit into the packed data destination.

公开(公告)号：US20230004389A1

公开(公告)日：2023-01-05

申请号：US17358231

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Joseph Williams ,  Zoran Zivkovic ,  Jian-Guo Chen ,  Hong Wan ,  David Dougherty ,  Jay O'neill

IPC: G06F9/30

Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

公开(公告)号：US09778902B2

公开(公告)日：2017-10-03

申请号：US13701374

申请日：2012-10-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Chengzhou Li ,  Albert Molina ,  Joseph H. Othmer ,  Steven C. Pinault ,  Meng-Lin Yu ,  Joseph Williams ,  Ramon Sanchez Perez ,  Jian-Guo Chen

IPC: G06F5/01 ,  G06F17/15 ,  G06F9/30 ,  H03H17/06 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  H04L25/02 ,  H04L25/03 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04L25/49 ,  H04B1/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

公开(公告)号：US12282774B2

公开(公告)日：2025-04-22

申请号：US17358231

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Joseph Williams ,  Zoran Zivkovic ,  Jian-Guo Chen ,  Hong Wan ,  David Dougherty ,  Jay O'neill

IPC: G06F9/30

Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

公开(公告)号：US20240220249A1

公开(公告)日：2024-07-04

申请号：US18147099

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Jian-Guo Chen ,  David Dougherty ,  Madihally Narasimha ,  Joseph Othmer ,  Hong Wan ,  Joseph Williams ,  Zoran Zivkovic

IPC: G06F9/30 ,  G06F30/343

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F30/343

Abstract: Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.