公开(公告)号：US09280315B2

公开(公告)日：2016-03-08

申请号：US13701376

申请日：2012-10-26

Applicant: Intel Corporation

Inventor： Kameran Azadet ,  Meng-Lin Yu ,  Joseph Othmer ,  Joseph Williams ,  Albert Molina

IPC: G06F17/15 ,  G06F5/01 ,  H04B1/04 ,  H04L1/00 ,  H04L27/233 ,  H04B1/62 ,  G06F9/30 ,  H04L25/02 ,  H04L25/03 ,  H03M3/00 ,  H03F1/02 ,  H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H04B1/00

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

Abstract translation: 提供了具有具有向量卷积函数的指令集的向量处理器。 所公开的向量处理器通过获得包括至少N1 + N2-1个输入样本的向量来执行输入信号和滤波器脉冲响应之间的卷积函数; 获得矢量的N2时移版本（包括零位版本），其中每个时移版本包括N1个样本; 以及通过N1系数的向量来执行向量的时移版本的加权和; 以及产生包括每个加权和的一个输出值的输出向量。 矢量处理器例如响应于具有矢量输入的一个或多个向量卷积软件指令来执行该方法。 矢量可以包括多个实数或复数输入样本，并且可以使用实数或复数的多个系数来表示滤波器脉冲响应。

公开(公告)号：US20240220249A1

公开(公告)日：2024-07-04

申请号：US18147099

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Jian-Guo Chen ,  David Dougherty ,  Madihally Narasimha ,  Joseph Othmer ,  Hong Wan ,  Joseph Williams ,  Zoran Zivkovic

IPC: G06F9/30 ,  G06F30/343

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F30/343

Abstract: Techniques are disclosed for the implementation of a programmable processing array architecture that realizes vectorized processing operations for a variety of applications. Such vectorized processing operations may include digital front end (DFE) processing operations, which include finite impulse response (FIR) filter processing operations. The programmable processing array architecture provides a front-end interconnection network that generates specific data sliding time window patterns in accordance with the particular DFE processing operation to be executed. The architecture enables the processed data generated in accordance with these sliding time window patterns to be fed to a set of multipliers and adders to generate output data. The architecture supports a wide range of processing operations to be performed via a single programmable processing array platform by leveraging the programmable nature of the array and the use of instruction sets.

公开(公告)号：US20240007337A1

公开(公告)日：2024-01-04

申请号：US17854155

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Sunitha Motipalli ,  Kameran Azadet ,  Albert Molina ,  Joseph Othmer ,  Kannan Rajamani

IPC: H04L27/26

CPC classification number: H04L27/2618 ,  H04L27/262 ,  H04L27/2615 ,  H04B1/0475

Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) technique that utilizes a cancellation pulse signal having a reduced length. The CFR technique may be applied to a signal to be transmitted, which may comprise a composite signal having one or more carrier signals. Each carrier signal of the composite signal may be filtered via a respective channel filter and then recombined to form the signal to be transmitted, on which the CFR operations are then applied. The length of the cancellation pulse signal is less than the number of taps of the channel filter with the largest number of taps. This reduction in cancellation pulse signal length significantly reduces the processing power required to perform the CFR operations while maintaining regulatory emissions compliance.

公开(公告)号：US20240004957A1

公开(公告)日：2024-01-04

申请号：US17854095

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Sunitha Motipalli ,  Kameran Azadet ,  Albert Molina ,  Joseph Othmer ,  Kannan Rajamani

IPC: G06K9/00

CPC classification number: G06K9/0053 ,  G06K9/0055

Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) algorithm that performs oversampling of an input signal and a cancellation pulse, and detects a set of peak samples in the upsampled input signal that exceed a predetermined threshold value. The peak samples are clustered such that a subset of the oversampled signal peaks are used to compute gain factors for the generation of a scaled truncated upsampled cancellation pulse. Several scaled truncated upsampled cancellation pulses are applied in parallel to perform peak cancellation of the highest peak in each cluster as part of an initial peak cancellation process. Any remaining peaks are canceled by iterative gain factors computation process. A final cancellation pulse is then generated by multiplying a cancellation pulse by the computed gain factors.