公开(公告)号：US20190253357A1

公开(公告)日：2019-08-15

申请号：US16160096

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Pravin PATHAK ,  Sundar VEDANTHAM ,  David SONNIER

IPC: H04L12/803 ,  H04L12/863 ,  H04L12/851

CPC classification number: H04L47/125 ,  H04L47/2441 ,  H04L47/6215 ,  H04L47/622 ,  H04L47/624 ,  H04L47/6255

Abstract: A computing platform includes a classifier to classify a packet and assign a processing load weight to the packet based at least in part on the packet classification; and a load balancer coupled to the classifier to compute a total processing load weight of a queue of a packet processing system and assign the packet to a queue with a lowest total processing load weight.