公开(公告)号：US12299105B2

公开(公告)日：2025-05-13

申请号：US18636479

申请日：2024-04-16

Applicant: Intel Corporation

Inventor： Bharat Pillilli ,  David W. Palmer ,  Nikola Radovanovic

IPC: G06F21/33 ,  G06F21/44 ,  G06F21/57 ,  G06F21/73

Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.

公开(公告)号：US20240370545A1

公开(公告)日：2024-11-07

申请号：US18636479

申请日：2024-04-16

Applicant: Intel Corporation

Inventor： Bharat Pillilli ,  David W. Palmer ,  Nikola Radovanovic

IPC: G06F21/33 ,  G06F21/44 ,  G06F21/57 ,  G06F21/73

Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.

公开(公告)号：US11983260B2

公开(公告)日：2024-05-14

申请号：US18296679

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Bharat Pillilli ,  David W. Palmer ,  Nikola Radovanovic

IPC: G06F21/33 ,  G06F21/44 ,  G06F21/57 ,  G06F21/73

CPC classification number: G06F21/33 ,  G06F21/44 ,  G06F21/572 ,  G06F21/73

Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.

公开(公告)号：US20210319088A1

公开(公告)日：2021-10-14

申请号：US17355378

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bharat Pillilli ,  David W. Palmer ,  Nikola Radovanovic

IPC: G06F21/33 ,  G06F21/73 ,  G06F21/57 ,  G06F21/44

Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.

公开(公告)号：US11693940B2

公开(公告)日：2023-07-04

申请号：US17355378

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bharat Pillilli ,  David W. Palmer ,  Nikola Radovanovic

IPC: G06F21/73 ,  G06F21/44 ,  G06F21/33 ,  G06F21/57

CPC classification number: G06F21/33 ,  G06F21/44 ,  G06F21/572 ,  G06F21/73

Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.

公开(公告)号：US20240195635A1

公开(公告)日：2024-06-13

申请号：US18064546

申请日：2022-12-12

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Ned M. Smith ,  Rajesh Poornachandran ,  Sunil K. Cheruvu ,  David W. Palmer

IPC: H04L9/32 ,  H04L9/08

CPC classification number: H04L9/3247 ,  H04L9/0825 ,  H04L9/0869

Abstract: The technology described herein includes a plurality of intellectual property (IP) blocks; and a host IP block, the host IP block including a primary root of trust (RoT) IP block (PRIB) coupled to the plurality of IP blocks, to receive a request from a computing system to establish a secure communications session with a selected one of a plurality of intellectual property (IP) blocks, authenticate and attest the computing system, sign evidence of the PRIB with a PRIB key, send the signed evidence of the PRIB to the computing system, and establish the secure communications session between the computing system and the selected IP block if the PRIB is trusted by the computing system based at least in part on the signed evidence of the PRIB.

公开(公告)号：US20230244772A1

公开(公告)日：2023-08-03

申请号：US18296679

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Bharat Pillilli ,  David W. Palmer ,  Nikola Radovanovic

IPC: G06F21/33 ,  G06F21/44 ,  G06F21/57 ,  G06F21/73

CPC classification number: G06F21/33 ,  G06F21/44 ,  G06F21/572 ,  G06F21/73

Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.