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公开(公告)号：US12299105B2
公开(公告)日：2025-05-13
申请号：US18636479
申请日：2024-04-16
Applicant: Intel Corporation
Inventor： Bharat Pillilli , David W. Palmer , Nikola Radovanovic
Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.
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Patent Agency Ranking
公开(公告)号：US20240370545A1
公开(公告)日：2024-11-07
申请号：US18636479
申请日：2024-04-16
Applicant: Intel Corporation
Inventor： Bharat Pillilli , David W. Palmer , Nikola Radovanovic
Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.
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公开(公告)号：US11693940B2
公开(公告)日：2023-07-04
申请号：US17355378
申请日：2021-06-23
Applicant: Intel Corporation
Inventor： Bharat Pillilli , David W. Palmer , Nikola Radovanovic
CPC classification number: G06F21/33 , G06F21/44 , G06F21/572 , G06F21/73
Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.
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公开(公告)号：US11983260B2
公开(公告)日：2024-05-14
申请号：US18296679
申请日：2023-04-06
Applicant: Intel Corporation
Inventor： Bharat Pillilli , David W. Palmer , Nikola Radovanovic
CPC classification number: G06F21/33 , G06F21/44 , G06F21/572 , G06F21/73
Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.
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公开(公告)号：US20210319088A1
公开(公告)日：2021-10-14
申请号：US17355378
申请日：2021-06-23
Applicant: Intel Corporation
Inventor： Bharat Pillilli , David W. Palmer , Nikola Radovanovic
Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.
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公开(公告)号：US20230244772A1
公开(公告)日：2023-08-03
申请号：US18296679
申请日：2023-04-06
Applicant: Intel Corporation
Inventor： Bharat Pillilli , David W. Palmer , Nikola Radovanovic
CPC classification number: G06F21/33 , G06F21/44 , G06F21/572 , G06F21/73
Abstract: A computer platform is disclosed. The computer platform comprises a central processing unit (CPU) including at least one socket having a plurality of tiles and control circuitry to partition the socket into a plurality of sub-sockets and assign a unique identity to each of the plurality of sub-sockets for security verification, wherein each sub-socket comprises at least one of the plurality of tiles to operate as a cluster of resources.
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