公开(公告)号：US11469299B2

公开(公告)日：2022-10-11

申请号：US16146785

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Dax Crum ,  Patrick Keys ,  Tahir Ghani ,  Susmita Ghose ,  Ted Cook, Jr.

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/683 ,  H01L21/8238 ,  H01L27/092

Abstract: Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11538806B2

公开(公告)日：2022-12-27

申请号：US16143951

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Rishabh Mehandru ,  Stephen Cea ,  Biswajeet Guha ,  Dax Crum ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

公开(公告)号：US11569370B2

公开(公告)日：2023-01-31

申请号：US16454408

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar ,  Biswajeet Guha ,  William Hsu ,  Dax Crum ,  Oleg Golonzka ,  Tahir Ghani ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L21/31 ,  H01L29/06 ,  H01L21/3105

Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.