公开(公告)号：US20230084463A1

公开(公告)日：2023-03-16

申请号：US17989951

申请日：2022-11-18

Applicant: Intel Corporation

Inventor： Sreejit CHAKRAVARTY ,  Rakesh KANDULA ,  Deep BAROT ,  Vishal VENDE

IPC: G06F3/06 ,  G11C29/12

Abstract: Runtime memory BIST techniques are described herein. In one example, a system such as an SoC includes logic to schedule runtime testing of the memory that is non-destructive in multiple phases. Running testing of memory in multiple phases includes triggering a memory built-in self-test (BIST) testing of a subset of memory locations in a phase, where the processing logic is to pause access to the memory during the phase. The processing logic can resume access to the memory between testing phases. The next region of the memory can be tested in the phase that follows. This process can continue until the entire memory is tested, without requiring the system to be powered down.