公开(公告)号：US20250068529A1

公开(公告)日：2025-02-27

申请号：US18236821

申请日：2023-08-22

Applicant: Intel Corporation

Inventor： Sreejit CHAKRAVARTY

IPC: G06F11/22

Abstract: Embodiments disclosed herein include apparatuses for improved testing between chips. In an embodiment, an apparatus comprises a plurality of transmit clusters on a first chip, where individual ones of the plurality of transmit clusters comprise a set of transmit lanes on the first chip. In an embodiment, a plurality of finite state machines (FSMs) are on the first chip, where individual ones of the plurality of transmit clusters comprise one of the plurality of FSMs. In an embodiment, a global transmit test generator is communicatively coupled to each of the set of transmit lanes on the first chip, and a global transmit expected response generator is communicatively coupled to each of the plurality of FSMs on the first chip.

公开(公告)号：US20190096503A1

公开(公告)日：2019-03-28

申请号：US15717721

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Sreejit CHAKRAVARTY ,  Fei SU ,  Puneet GUPTA ,  Wei Ming LIM ,  Terrence Huat Hin TAN ,  Amit SANGHANI ,  Anubhav SINHA ,  Sudheer V BADANA ,  Rakesh KANDULA ,  Adithya B. S.

IPC: G11C29/12 ,  G11C29/48 ,  H01L23/538 ,  H01L25/065 ,  H03K17/00 ,  H03K17/56

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

公开(公告)号：US20230084463A1

公开(公告)日：2023-03-16

申请号：US17989951

申请日：2022-11-18

Applicant: Intel Corporation

Inventor： Sreejit CHAKRAVARTY ,  Rakesh KANDULA ,  Deep BAROT ,  Vishal VENDE

IPC: G06F3/06 ,  G11C29/12

Abstract: Runtime memory BIST techniques are described herein. In one example, a system such as an SoC includes logic to schedule runtime testing of the memory that is non-destructive in multiple phases. Running testing of memory in multiple phases includes triggering a memory built-in self-test (BIST) testing of a subset of memory locations in a phase, where the processing logic is to pause access to the memory during the phase. The processing logic can resume access to the memory between testing phases. The next region of the memory can be tested in the phase that follows. This process can continue until the entire memory is tested, without requiring the system to be powered down.