公开(公告)号：US20240264231A1

公开(公告)日：2024-08-08

申请号：US18106244

申请日：2023-02-06

Applicant: Intel Corporation

Inventor： Rakesh KANDULA ,  Michaël Carl NÈVE DE MÉVERGNIES

IPC: G01R31/3185 ,  G01R31/317 ,  G06F21/72

CPC classification number: G01R31/318588 ,  G01R31/31725 ,  G06F21/72

Abstract: Examples include techniques for infield testing of cryptographic circuitry located on a die. The infield testing to include providing a pass or fail status of an infield test scan of the cryptographic circuitry based on comparing an output generated by the cryptographic circuitry during a test run to a signature. The output generated by the cryptographic circuitry is in response to an input generated by a linear-feedback shift register during the test run.

公开(公告)号：US20250110175A1

公开(公告)日：2025-04-03

申请号：US18374198

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rakesh KANDULA ,  Sankaran M. MENON ,  Rolf KUEHNIS

IPC: G01R31/319 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185

Abstract: Methods, apparatus, and computer programs are disclosed to detect computing system hardware defects using a portable storage device. In one embodiment, a method includes accessing a portable storage device to obtain an identifier and a set of test patterns to test a set of circuits of a computing system, the identifier to map to the set of test patterns. The method further includes determining that the set of test patterns is to be executed on the computing system based on the identifier to be obtained from accessing the portable storage device. Responsive to the determination, and executing the set of test patterns loaded from the portable storage device on the set of circuits of the computing system to detect one or more hardware defects of the set of circuits.

公开(公告)号：US20240103077A1

公开(公告)日：2024-03-28

申请号：US17954658

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Rakesh KANDULA ,  Sankaran MENON ,  Rolf KUEHNIS

IPC: G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/318533 ,  G01R31/31907 ,  G01R31/31924

Abstract: Time to read the data registers in a remote Test Access Port (TAP) in a subsystem in a System-on-Chip (SoC) is reduced by reading multiple data registers in remote Test Access Ports in parallel. A Test Access Port Bridge provides access to multiple same width data registers in parallel. The same width data registers can be for the same function or different functions. The subsystems with a remote Test Access Port in the SoC can include Peripheral Component Interconnect Express (PCIe), Voltage Droop Monitors (VDMs), In-Die Variation (IDV) Monitor fub-lets, Temperature Sensors, Performance Monitors and telemetry subsystems.

公开(公告)号：US20190096503A1

公开(公告)日：2019-03-28

申请号：US15717721

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Sreejit CHAKRAVARTY ,  Fei SU ,  Puneet GUPTA ,  Wei Ming LIM ,  Terrence Huat Hin TAN ,  Amit SANGHANI ,  Anubhav SINHA ,  Sudheer V BADANA ,  Rakesh KANDULA ,  Adithya B. S.

IPC: G11C29/12 ,  G11C29/48 ,  H01L23/538 ,  H01L25/065 ,  H03K17/00 ,  H03K17/56

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

公开(公告)号：US20250111113A1

公开(公告)日：2025-04-03

申请号：US18375349

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Rakesh KANDULA ,  Ravishankar D

IPC: G06F30/327

Abstract: Methods that are useful in semiconductor chip design are presented. A microarchitectural structured flow chart can be processed and converted into register transfer level hardware description language code. Processing of the flow chart can include detecting shapes, lines, colors, and text. The shapes that are detected can be rounded, rhombus, and rectangle and a rounded shape can represent a state, a rhombus can represent a decision, and a rectangle can represent an assignment for a finite state machine.

公开(公告)号：US20240219462A1

公开(公告)日：2024-07-04

申请号：US18091060

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Rakesh KANDULA ,  Edward BRAZIL ,  Amir ZALTZMAN ,  Alon PERETZ ,  Alexander SEREBRYANIK ,  Chai ZIV ,  Nir BARUCH ,  Gilad SHAYEVITZ

IPC: G01R31/317

CPC classification number: G01R31/31705

Abstract: Examples include techniques for debug, survivability, and infield testing of a system-on-a-chip (SoC) or system-on-a-package (SoP) that can be configured as a processor. The techniques include using an agent coupled with a network-on-chip (NoC) fabric to launch transaction over the NoC fabric to test or debug agents, devices, or devices coupled to the SoC or SoP and/or interconnected to the NoC fabric.

公开(公告)号：US20230084463A1

公开(公告)日：2023-03-16

申请号：US17989951

申请日：2022-11-18

Applicant: Intel Corporation

Inventor： Sreejit CHAKRAVARTY ,  Rakesh KANDULA ,  Deep BAROT ,  Vishal VENDE

IPC: G06F3/06 ,  G11C29/12

Abstract: Runtime memory BIST techniques are described herein. In one example, a system such as an SoC includes logic to schedule runtime testing of the memory that is non-destructive in multiple phases. Running testing of memory in multiple phases includes triggering a memory built-in self-test (BIST) testing of a subset of memory locations in a phase, where the processing logic is to pause access to the memory during the phase. The processing logic can resume access to the memory between testing phases. The next region of the memory can be tested in the phase that follows. This process can continue until the entire memory is tested, without requiring the system to be powered down.