公开(公告)号：US20190250697A1

公开(公告)日：2019-08-15

申请号：US16396557

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Adrian MOCANU ,  Andrew MORNING-SMITH ,  Zeljko ZUPANC ,  Derrick WILSON

IPC: G06F1/3296 ,  G06F3/06 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.