公开(公告)号：US20190278503A1

公开(公告)日：2019-09-12

申请号：US16425883

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Sowmiya JAYACHANDRAN ,  Andrew MORNING-SMITH ,  Brian R. MCFARLANE ,  William T. GLENNAN ,  Emily P. CHUNG

IPC: G06F3/06 ,  G06F1/30 ,  G06F11/30

Abstract: A method is described. The method includes performing write operations on a plurality of NVRAM semiconductor chips of a memory module while tracking power budget headroom for performing the write operations and while monitoring current draw on a supply voltage rail that is coupled to the plurality of NVRAM semiconductor chips. The method further includes detecting the current draw has reached a threshold. The method further includes ceasing or diminishing the write operations in response to the detecting.

公开(公告)号：US20170177374A1

公开(公告)日：2017-06-22

申请号：US14975272

申请日：2015-12-18

Applicant: INTEL CORPORATION

Inventor： Andrew MORNING-SMITH ,  Adrian MOCANU ,  Zeljko ZUPANC ,  Mike M. NGO

IPC: G06F9/44 ,  G06F1/30 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F11/1441 ,  G06F1/263 ,  G06F1/305 ,  G06F9/442 ,  G06F13/4022

Abstract: Provided is a memory device, comprising a non-volatile memory, an energy store coupled to an input power module of the non-volatile memory, and a power management module configurable to determine whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line. Provided also is a computational device that includes the memory device. Provided also is a method in which a power management module of the memory device determines whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line.

公开(公告)号：US20190041938A1

公开(公告)日：2019-02-07

申请号：US16047358

申请日：2018-07-27

Applicant: Intel Corporation

Inventor： Zeljko ZUPANC ,  Andrew MORNING-SMITH ,  Mary GOODMAN ,  Alice ALLEN ,  Simon RAMAGE ,  Justin ELKOW

IPC: G06F1/30 ,  H02J7/00 ,  G01R31/40 ,  G01R31/36

Abstract: A nonvolatile storage device includes a power management system with a power loss imminent (PLI) capacitor to provide backup energy in case system power is lost. The power management system includes a circuit with a charging path for the PLI capacitor that includes a series current-limiting circuit, and a diode coupled in parallel with the current-limiting circuit, the diode having a cathode coupled to the charging circuit and an anode to couple to the PLI capacitor.

公开(公告)号：US20170069356A1

公开(公告)日：2017-03-09

申请号：US14845373

申请日：2015-09-04

Applicant: Intel Corporation

Inventor： Kai-Uwe SCHMIDT ,  Andrew MORNING-SMITH ,  Adrian MOCANU ,  Mike M. NGO

IPC: G11C5/14 ,  H02J7/00

CPC classification number: G11C5/148 ,  G01R21/006 ,  G01R27/2688 ,  G01R31/3004 ,  G01R31/44 ,  G11C5/141 ,  G11C29/02 ,  G11C29/021 ,  G11C29/50 ,  G11C2029/5002 ,  H02J7/0068 ,  H02J7/345

Abstract: These present disclosure provides techniques to determine the capacitance of a power loss capacitor based on voltage ripple. The power loss capacitor may be a power loss capacitor for a power loss shutdown system of a solid state drive. The capacitance may be determined as a function of the voltage ripple and a period of the voltage ripple during a natural discharge and a controlled discharge of the power loss capacitor.

Abstract translation: 这些本公开提供了基于电压纹波确定功率损耗电容器的电容的技术。 功率损耗电容器可以是用于固态驱动器的功率损耗关断系统的功率损耗电容器。 电容可以根据电压波动以及在自然放电期间的电压纹波的周期以及功率损耗电容器的受控放电来确定。

公开(公告)号：US20190250697A1

公开(公告)日：2019-08-15

申请号：US16396557

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Adrian MOCANU ,  Andrew MORNING-SMITH ,  Zeljko ZUPANC ,  Derrick WILSON

IPC: G06F1/3296 ,  G06F3/06 ,  G06F1/3234

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.

公开(公告)号：US20190116660A1

公开(公告)日：2019-04-18

申请号：US16218344

申请日：2018-12-12

Applicant: INTEL CORPORATION

Inventor： Andrew MORNING-SMITH ,  Eugene LIM ,  Meng ZHAI

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/028 ,  H05K1/0278 ,  H05K1/189 ,  H05K3/4691 ,  H05K2201/055 ,  H05K2201/10159

Abstract: Embodiments include devices and method related to a foldable printed circuit board that may be used in SSD applications. One embodiment relates to a foldable printed circuit board comprising a first rigid portion, a second rigid portion, and a first flexible region coupling the first rigid portion to the second rigid portion. The foldable printed circuit board also includes a third rigid portion and a second flexible region coupling the second rigid portion to the third rigid portion, wherein the first rigid portion and the third rigid portion each have a width that is less than that of the second rigid portion. Other embodiments are described and claimed.