公开(公告)号：US09311239B2

公开(公告)日：2016-04-12

申请号：US13976313

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Niranjan Cooray ,  Steffen Kosinski ,  Rami May ,  Doron Gershon ,  Jaroslaw Topp ,  Varun Mohandru

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0811 ,  G06F12/0864 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/65 ,  G06F2212/681 ,  Y02D10/13

Abstract: A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure may store vectors in an L1 tag array to enable an L1 tag lookup that has fewer bits per entry and consumes less power. The vectors may identify entries in a translation lookaside buffer tag array. When a virtual memory address associated with a memory access instruction hits in the translation lookaside buffer, the translation lookaside buffer may generate a vector identifying the set and the way of the translation lookaside buffer entry that matched. This vector may then be compared to a group of vectors stored in a set of the L1 tag arrays to determine whether the virtual memory address hits in the L1 cache.

Abstract translation: 一种用于实现高速缓冲存储器的标签结构的系统和方法，其包括多路组合关联翻译后备缓冲器。 标签结构可以将向量存储在L1标签阵列中，以便能够进行每个条目具有较少位的L1标签查找并消耗更少的功率。 向量可以标识翻译后备缓冲器标签阵列中的条目。 当与存储器访问指令相关联的虚拟存储器地址在翻译后备缓冲器中时，翻译后备缓冲器可以生成标识集合的向量和匹配的翻译后备缓冲器条目的方式。 然后将该向量与存储在一组L1标签阵列中的一组矢量进行比较，以确定虚拟存储器地址是否在L1高速缓存中命中。

公开(公告)号：US20150220436A1

公开(公告)日：2015-08-06

申请号：US13976313

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： Niranjan Cooray ,  Steffen Kosinski ,  Rami May ,  Doron Gershon ,  Jaroslaw Topp ,  Varun Mohandru

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0811 ,  G06F12/0864 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1045 ,  G06F2212/283 ,  G06F2212/6032 ,  G06F2212/65 ,  G06F2212/681 ,  Y02D10/13

Abstract: A system and method to implement a tag structure for a cache memory that includes a multi-way, set-associative translation lookaside buffer. The tag structure may store vectors in an L1 tag array to enable an L1 tag lookup that has fewer bits per entry and consumes less power. The vectors may identify entries in a translation lookaside buffer tag array. When a virtual memory address associated with a memory access instruction hits in the translation lookaside buffer, the translation lookaside buffer may generate a vector identifying the set and the way of the translation lookaside buffer entry that matched. This vector may then be compared to a group of vectors stored in a set of the L1 tag arrays to determine whether the virtual memory address hits in the L1 cache.

Abstract translation: 一种用于实现高速缓冲存储器的标签结构的系统和方法，其包括多路组合关联翻译后备缓冲器。 标签结构可以将向量存储在L1标签阵列中，以便能够进行每个条目具有较少位的L1标签查找并消耗更少的功率。 向量可以标识翻译后备缓冲器标签阵列中的条目。 当与存储器访问指令相关联的虚拟存储器地址在翻译后备缓冲器中时，翻译后备缓冲器可以生成标识集合的向量和匹配的翻译后备缓冲器条目的方式。 然后将该向量与存储在一组L1标签阵列中的一组矢量进行比较，以确定虚拟存储器地址是否在L1高速缓存中命中。