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公开(公告)号：US20150379668A1
公开(公告)日：2015-12-31
申请号：US14319099
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： ELIEZER WEISSMANN , ARIK GIHON , EFRAIM ROTEM , PAUL S. DIEFENBAUGH , ERIC C. SAMSON , MICHAEL MISHAELI , YONI AIZIK , CHEN RANEL
CPC classification number: G06F9/5044 , G06F3/14 , G06F9/5083 , G09G2360/08
Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.
Abstract translation: 一种用于确定线程执行并行性的装置和方法。 例如，根据一个实施例的处理器包括：多个核，用于执行多个线程; 多个计数器，用于收集与所述多个核上的所述多个线程的执行相关的数据; 依赖关系分析模块，用于分析与线程的执行有关的数据，并且响应地确定线程间相关性的级别; 以及控制模块，用于基于确定的线程间依赖性水平来响应地调整多个核心的操作。
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公开(公告)号：US20220269330A1
公开(公告)日：2022-08-25
申请号：US17662852
申请日：2022-05-11
Applicant: Intel Corporation
Inventor： AHMED ABOU-ALFOTOUH , PHANI KUMAR KANDULA , LINDA L. HURD , ERIC C. SAMSON , SRIKRISHNAN VENKATARAMAN
IPC: G06F1/3234
Abstract: A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.
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公开(公告)号：US20210405729A1
公开(公告)日：2021-12-30
申请号：US16914290
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： AHMED ABOU-ALFOTOUH , PHANI KUMAR KANDULA , LINDA L. HURD , ERIC C. SAMSON , SRIKRISHNAN VENKATARAMAN
IPC: G06F1/3234
Abstract: A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.
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