公开(公告)号：US11869232B2

公开(公告)日：2024-01-09

申请号：US18151914

申请日：2023-01-09

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06V10/82 ,  G06N3/04 ,  G06F30/33 ,  G06V10/44 ,  G06V10/94

CPC classification number: G06V10/82 ,  G06F30/33 ,  G06N3/04 ,  G06V10/454 ,  G06V10/955

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

公开(公告)号：US20240104916A1

公开(公告)日：2024-03-28

申请号：US18519674

申请日：2023-11-27

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06V10/82 ,  G06F30/33 ,  G06N3/04 ,  G06V10/44 ,  G06V10/94

CPC classification number: G06V10/82 ,  G06F30/33 ,  G06N3/04 ,  G06V10/454 ,  G06V10/955

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

公开(公告)号：US10430313B2

公开(公告)日：2019-10-01

申请号：US14864597

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Norbert Schulz ,  Frank Penczek ,  Joseph E. Wylder ,  Eran Geva

IPC: G06F1/00 ,  G06F11/34

Abstract: Generally, this disclosure provides systems, methods and computer readable media for correlation of OS and hardware events to provide a corrected trace sequence. A system may include a processor configured to receive an OS event at a first time, generate a first timestamp based on a first clock associated with the OS, buffer the OS event until a second time, and generate a second timestamp based on the first clock. The system may also include a trace generation circuit configured to receive the OS event from the processor after the second time and generate a third timestamp based on a second clock associated with the trace generation circuit. The system may further include a trace correction circuit configured to calculate a corrected timestamp for the OS event based on differences between the first, second and third timestamps and further based on the relative frequency between the first and second clocks.

公开(公告)号：US20190180168A1

公开(公告)日：2019-06-13

申请号：US16266880

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06N3/04 ,  G06F9/30 ,  G06F17/50

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

公开(公告)号：US11562200B2

公开(公告)日：2023-01-24

申请号：US16266880

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06N3/04 ,  G06F30/33

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

公开(公告)号：US12211260B2

公开(公告)日：2025-01-28

申请号：US18519674

申请日：2023-11-27

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06V10/82 ,  G06F30/33 ,  G06N3/04 ,  G06V10/44 ,  G06V10/94

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

公开(公告)号：US20230215158A1

公开(公告)日：2023-07-06

申请号：US18151914

申请日：2023-01-09

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06V10/82 ,  G06N3/04 ,  G06F30/33 ,  G06V10/44 ,  G06V10/94

CPC classification number: G06V10/82 ,  G06N3/04 ,  G06F30/33 ,  G06V10/454 ,  G06V10/955

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.