公开(公告)号：US20230209797A1

公开(公告)日：2023-06-29

申请号：US17560779

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Smita Shridharan ,  Zheng Guo ,  Eric Karl ,  Tahir Ghani

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.