公开(公告)号：US20230209798A1

公开(公告)日：2023-06-29

申请号：US17560913

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Mohammad Hasan ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L27/1108 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/66742 ,  H01L29/42392

Abstract: Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors having a different number of active channel regions than the number of active channel regions in pull-down transistors. A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.

公开(公告)号：US20240008239A1

公开(公告)日：2024-01-04

申请号：US17856870

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand Murthy ,  Rajabali Koduri ,  Clifford Ong ,  Sagar Suthram

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419

Abstract: Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.

公开(公告)号：US20230209799A1

公开(公告)日：2023-06-29

申请号：US17560927

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Dan Lavric ,  Leonard Guler ,  YenTing Chiu ,  Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1108 ,  H01L29/4908 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/78696 ,  H01L29/6684 ,  H01L29/66742

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

公开(公告)号：US11152060B2

公开(公告)日：2021-10-19

申请号：US16449285

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Xiaofei Wang ,  Dinesh Somasekhar ,  Clifford Ong ,  Eric A Karl ,  Zheng Guo ,  Gordon Carskadon

IPC: G11C11/56 ,  G11C17/12 ,  H01L27/112

Abstract: Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.

公开(公告)号：US20210098059A1

公开(公告)日：2021-04-01

申请号：US17117795

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Yu-Lin Chao ,  Dmitri E. Nikonov ,  Ian Young ,  Eric A. Karl

IPC: G11C11/56 ,  G11C7/10 ,  G06F3/06

Abstract: Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

公开(公告)号：US12009026B2

公开(公告)日：2024-06-11

申请号：US17117795

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Yu-Lin Chao ,  Dmitri E. Nikonov ,  Ian Young ,  Eric A. Karl

IPC: G11C11/54 ,  G06F3/06 ,  G11C7/10 ,  G11C11/56 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C11/56 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/1051 ,  G11C7/1096 ,  G11C7/06 ,  G11C7/222

Abstract: Systems and methods for precision writing of weight values to a memory capable of storing multiple levels in each cell are disclosed. Embodiments include logic to compare an electrical parameter read from a memory cell with a base reference and an interval reference, and stop writing once the electrical parameter is between the base reference and the base plus the interval reference. The interval may be determined using a greater number of levels than the number of stored levels, to prevent possible overlap of read values of the electrical parameter due to memory device variations.

公开(公告)号：US20230320057A1

公开(公告)日：2023-10-05

申请号：US17711875

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Mohit Haran ,  Smita Shridharan ,  Reken Patel ,  Charles Wallace ,  Chanaka Munasinghe ,  Pratik Patel

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/412 ,  H01L21/768 ,  H01L23/522 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  G11C11/412 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/42392

Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.

公开(公告)号：US20230209797A1

公开(公告)日：2023-06-29

申请号：US17560779

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Smita Shridharan ,  Zheng Guo ,  Eric Karl ,  Tahir Ghani

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.