公开(公告)号：US12131991B2

公开(公告)日：2024-10-29

申请号：US17671543

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5283 ,  H01L29/41725 ,  H01L29/4232

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US20240241446A1

公开(公告)日：2024-07-18

申请号：US18620262

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Marvin Paik ,  Charles H. Wallace ,  Leonard Guler ,  Elliot N. Tan ,  Shengsi Liu ,  Vivek Vishwakarma ,  Izabela Samek ,  Mohammadreza Soleymaniha

IPC: G03F7/20 ,  G03F7/00 ,  H01L21/027

CPC classification number: G03F7/2022 ,  G03F7/2004 ,  G03F7/201 ,  G03F7/70033 ,  G03F7/7005 ,  G03F7/70525 ,  G03F7/7055 ,  G03F7/70725 ,  H01L21/0275

Abstract: Apparatus and methods are disclosed. An example lithography apparatus includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.

公开(公告)号：US11901458B2

公开(公告)日：2024-02-13

申请号：US17850799

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Bruce E. Beattie ,  Leonard Guler ,  Biswajeet Guha ,  Jun Sung Kang ,  William Hsu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/6681 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

公开(公告)号：US20230209799A1

公开(公告)日：2023-06-29

申请号：US17560927

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Dan Lavric ,  Leonard Guler ,  YenTing Chiu ,  Smita Shridharan ,  Zheng Guo ,  Eric A. Karl ,  Tahir Ghani

IPC: H01L27/11 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1108 ,  H01L29/4908 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/78696 ,  H01L29/6684 ,  H01L29/66742

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising pass-gate transistors and pull-down transistors having different threshold voltages (Vt). A pass-gate transistor with a higher Vt than the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a different amount of a dipole dopant source material is deposited as part of the gate insulator for the pull-down transistor than for the pass-gate transistor, reducing the Vt of the pull-down transistor accordingly. In some examples, an N-dipole dopant source material is removed from the pass-gate transistor prior to a drive/activation anneal is performed. After drive/activation, the N-dipole dopant source material may be removed from the pull-down transistor and a same gate metal deposited over both the pass-gate and pull-down transistors.

公开(公告)号：US11251117B2

公开(公告)日：2022-02-15

申请号：US16562346

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US20240404917A1

公开(公告)日：2024-12-05

申请号：US18204864

申请日：2023-06-01

Applicant: Intel Corporation

Inventor： Sikandar Abbas ,  Chanaka Munasinghe ,  Leonard Guler ,  Reza Bayati ,  Madeleine Stolt ,  Makram Abd El Qader ,  Pratik Patel ,  Anindya Dasgupta

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.

公开(公告)号：US20220173034A1

公开(公告)日：2022-06-02

申请号：US17671543

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US11342411B2

公开(公告)日：2022-05-24

申请号：US16023511

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： William Hsu ,  Biswajeet Guha ,  Leonard Guler ,  Souvik Chakrabarty ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  B82Y10/00

Abstract: A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain.

公开(公告)号：US20210074632A1

公开(公告)日：2021-03-11

申请号：US16562346

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/423 ,  H01L29/417

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US20240332290A1

公开(公告)日：2024-10-03

申请号：US18129700

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Patrick Morrow ,  Nikhil Mehta ,  Leonard Guler ,  Sudipto Naskar ,  Alison Davis ,  Dan Lavric ,  Matthew Prince ,  Jeanne Luce ,  Charles Wallace ,  Cortnie Vogelsberg ,  Rajaram Pai ,  Caitlin Kilroy ,  Jojo Amonoo ,  Sean Pursel ,  Yulia Gotlib

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/32139 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.