公开(公告)号：US20210034344A1

公开(公告)日：2021-02-04

申请号：US17074336

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Diego Luis Caballero de Gea ,  Hideki Ido ,  Eric N. Garcia

IPC: G06F8/41

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve loop optimization with predictable recurring memory reads (PRMRs). An example apparatus includes memory, and first processor circuitry to execute first instructions to at least identify one or more optimizations to convert a first loop into a second loop based on converting PRMRs of the first loop into loop-invariant PRMRs, the converting of the PRMRs in response to a quantity of the PRMRs satisfying a threshold, the second loop to execute in a single iteration corresponding to a quantity of iterations of the first loop, determine one or more optimization parameters based on the one or more optimizations, and compile second instructions based on the first processor circuitry processing the first loop based on the one or more optimization parameters associated with the one or more optimizations, the second instructions to be executed by the first or second processor circuitry.

公开(公告)号：US20190042224A1

公开(公告)日：2019-02-07

申请号：US16128275

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Diego Luis Caballero de Gea ,  Hideki Ido ,  Eric N. Garcia

IPC: G06F8/41

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve loop optimization with predictable recurring memory reads (PRMRs). An example apparatus includes an optimizer including an optimization scenario manager to generate an optimization plan associated with a loop and corresponding optimization parameters, the optimization plan including a set of one or more optimizations, an optimization scenario analyzer to identify the optimization plan as a candidate optimization plan when a quantity of PRMRs included in the loop is greater than a threshold, and a parameter calculator to determine the optimization parameters based on the candidate optimization plan, and a code generator to generate instructions to be executed by a processor, the instructions based on processing the loop with the one or more optimizations included in the candidate optimization plan.

公开(公告)号：US11442713B2

公开(公告)日：2022-09-13

申请号：US17074336

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Diego Luis Caballero de Gea ,  Hideki Ido ,  Eric N. Garcia

IPC: G06F9/44 ,  G06F8/41

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve loop optimization with predictable recurring memory reads (PRMRs). An example apparatus includes memory, and first processor circuitry to execute first instructions to at least identify one or more optimizations to convert a first loop into a second loop based on converting PRMRs of the first loop into loop-invariant PRMRs, the converting of the PRMRs in response to a quantity of the PRMRs satisfying a threshold, the second loop to execute in a single iteration corresponding to a quantity of iterations of the first loop, determine one or more optimization parameters based on the one or more optimizations, and compile second instructions based on the first processor circuitry processing the first loop based on the one or more optimization parameters associated with the one or more optimizations, the second instructions to be executed by the first or second processor circuitry.

公开(公告)号：US10853043B2

公开(公告)日：2020-12-01

申请号：US16128275

申请日：2018-09-11

Applicant: Intel Corporation

Inventor： Diego Luis Caballero de Gea ,  Hideki Ido ,  Eric N. Garcia

IPC: G06F8/41

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve loop optimization with predictable recurring memory reads (PRMRs). An example apparatus includes an optimizer including an optimization scenario manager to generate an optimization plan associated with a loop and corresponding optimization parameters, the optimization plan including a set of one or more optimizations, an optimization scenario analyzer to identify the optimization plan as a candidate optimization plan when a quantity of PRMRs included in the loop is greater than a threshold, and a parameter calculator to determine the optimization parameters based on the candidate optimization plan, and a code generator to generate instructions to be executed by a processor, the instructions based on processing the loop with the one or more optimizations included in the candidate optimization plan.

公开(公告)号：US20180181404A1

公开(公告)日：2018-06-28

申请号：US15391915

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Hideki Saito Ido ,  Eric N. Garcia ,  Xinmin Tian ,  Milind B. Girkar ,  James Brodman

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3844 ,  G06F9/30058 ,  G06F9/3806 ,  G06F15/76

Abstract: In one example, a system for generating vector based selection control statements can include a processor to determine a vector cost of the selection control statement is below a scalar cost and determine the selection control statement is to be executed in a sorted order based on dependencies between branch instructions of the selection control statement. The processor can also determine a program ordering of labels of the selection control statement does not match a mathematical ordering of the labels and execute the selection control statement with a vector of values, wherein the selection control statement is to be executed based on a jump table and a sorted unique value technique, wherein the sorted unique value technique comprises selecting at least one of the plurality of branch instructions from the jump table.