公开(公告)号：US20230019974A1

公开(公告)日：2023-01-19

申请号：US17957719

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Srinivasan S. IYENGAR ,  Erik MCSHANE ,  Edward HO ,  Noam ELATI

IPC: G06F1/324 ,  H04L49/1546

Abstract: A network device can place some or all of the packet processing pipeline into a low-power state for detected idle intervals of sufficient duration. The network device detects idleness greater than a critical duration and automatically engages a low-power mode involving clock throttling and/or clock gating. The power savings in the packet processing pipeline in the network device is based on the average long-term residency in idleness. The idle power is reduced for the packet processing pipeline in the network device by detecting average long-term idleness as a function of the minimum latency of the packet processing pipeline, which is used to reduce the clock rate of the packet processing pipeline, thereby resulting in power savings for the network device.