公开(公告)号：US20240039867A1

公开(公告)日：2024-02-01

申请号：US18378463

申请日：2023-10-10

申请人： Marvell Asia PTE, LTD

发明人： Guy Townsend Hutchison ,  Sachin Ramesh Gandhi ,  Tsahi Daniel ,  Gerald Schmidt ,  Albert Fishman ,  Martin Leslie White ,  Zubin Shah

IPC分类号： H04L49/109 ,  G06F3/06 ,  H04L45/64 ,  H04L45/745 ,  H04L49/1546 ,  H04L69/22 ,  H04L49/00 ,  G06F16/00 ,  H04L45/74 ,  G06F40/205 ,  H04L67/63

CPC分类号： H04L49/109 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0673 ,  G06F3/0656 ,  H04L45/64 ,  H04L45/745 ,  H04L49/1546 ,  H04L69/22 ,  H04L49/3018 ,  G06F16/00 ,  H04L45/74 ,  G06F40/205 ,  H04L67/63

摘要： A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

公开(公告)号：US11824796B2

公开(公告)日：2023-11-21

申请号：US16992978

申请日：2020-08-13

申请人： Marvell Asia PTE, LTD

发明人： Guy Townsend Hutchison ,  Sachin Ramesh Gandhi ,  Tsahi Daniel ,  Gerald Schmidt ,  Albert Fishman ,  Martin Leslie White ,  Zubin Shah

IPC分类号： H04L12/28 ,  H04L49/109 ,  G06F3/06 ,  H04L45/64 ,  H04L45/745 ,  H04L49/1546 ,  H04L69/22 ,  H04L49/00 ,  G06F16/00 ,  H04L45/74 ,  G06F40/205 ,  H04L67/63

CPC分类号： H04L49/109 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0673 ,  G06F16/00 ,  G06F40/205 ,  H04L45/64 ,  H04L45/74 ,  H04L45/745 ,  H04L49/1546 ,  H04L49/3018 ,  H04L67/63 ,  H04L69/22

摘要： A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

公开(公告)号：US20220345405A1

公开(公告)日：2022-10-27

申请号：US17859722

申请日：2022-07-07

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart

IPC分类号： H04L45/745 ,  H04L45/00 ,  H04L49/101 ,  H04L45/64 ,  H04L49/1546 ,  H04L69/22

摘要： Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

公开(公告)号：US20240039791A1

公开(公告)日：2024-02-01

申请号：US18239084

申请日：2023-08-28

申请人： Nicira, Inc.

发明人： Martin Casado ,  Teemu Koponen ,  Pankaj Thakkar

IPC分类号： H04L41/0893 ,  H04L49/1546 ,  H04L45/586 ,  H04L49/00 ,  G06F15/173 ,  H04L12/46 ,  H04L47/783 ,  H04L45/00 ,  H04L41/0896 ,  H04L61/5007 ,  H04L45/02 ,  H04L41/0816 ,  H04L41/0853

CPC分类号： H04L41/0893 ,  H04L49/1546 ,  H04L45/586 ,  H04L49/3063 ,  G06F15/17312 ,  H04L12/4633 ,  H04L47/783 ,  H04L45/00 ,  H04L49/00 ,  H04L41/0896 ,  H04L61/5007 ,  H04L45/02 ,  H04L49/70 ,  H04L41/0816 ,  H04L41/0853 ,  G06F11/07

摘要： Some embodiments provide a system that includes a set of network controllers for receiving definitions of first and second logical switching elements. The system includes several managed switching elements. The set of network controllers configure the several managed switching elements to implement the defined first and second logical switching elements. The system includes several network hosts that are each (1) communicatively coupled to one of the several managed switching elements and (2) associated with one of the first and second logical switching elements. Network data communicated between network hosts associated with the first logical switching element are isolated from network data communicated between network hosts associated with the second logical switching element.

公开(公告)号：US11736413B2

公开(公告)日：2023-08-22

申请号：US17149760

申请日：2021-01-15

申请人： VMware, Inc.

发明人： Yong Wang ,  Boon Seong Ang ,  Wenyi Jiang ,  Guolin Yang

IPC分类号： H04L49/1546 ,  H04L69/22 ,  H04L49/00 ,  H04L9/06 ,  H04L9/40 ,  H04L45/7453

CPC分类号： H04L49/3063 ,  H04L9/0643 ,  H04L45/7453 ,  H04L63/20 ,  H04L69/22 ,  H04L2212/00

摘要： Example methods and systems for a programmable virtual network interface controller (VNIC) to perform packet processing are described. In one example, the programmable VNIC may modify a packet processing pipeline based on the instruction. The modification may include injecting a second packet processing stage among the multiple first packet processing stages of the packet processing pipeline. In response to detecting an ingress packet that requires processing by the programmable VNIC, the ingress packet may be steered towards the modified packet processing pipeline. The ingress packet may then be processed using the modified packet processing pipeline by performing the second packet processing stage (a) to bypass at least one of the multiple first processing stages, or (b) in addition to the multiple first processing stages.

公开(公告)号：US11425038B2

公开(公告)日：2022-08-23

申请号：US16695044

申请日：2019-11-25

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart

IPC分类号： H04L12/741 ,  H04L12/933 ,  H04L45/745 ,  H04L45/00 ,  H04L49/101 ,  H04L45/64 ,  H04L49/1546 ,  H04L69/22 ,  H04L45/74 ,  H04L45/42

摘要： Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

公开(公告)号：US11411870B2

公开(公告)日：2022-08-09

申请号：US16573847

申请日：2019-09-17

申请人： Barefoot Networks, Inc.

发明人： Patrick Bosshart

IPC分类号： H04L12/741 ,  H04L12/933 ,  H04L45/745 ,  H04L45/00 ,  H04L49/101 ,  H04L45/64 ,  H04L49/1546 ,  H04L69/22 ,  H04L45/74 ,  H04L45/42

摘要： Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

公开(公告)号：US11876696B2

公开(公告)日：2024-01-16

申请号：US17463202

申请日：2021-08-31

申请人： Pensando Systems Inc.

发明人： Vijay Srinivasan ,  Sarat Kamisetty ,  Krishna Doddapaneni ,  John Cruz ,  Loganathan Nallusamy

IPC分类号： H04L43/10 ,  H04L41/12 ,  H04L43/062 ,  H04L49/00 ,  H04L69/22 ,  H04L43/18 ,  H04L49/1546 ,  H04L49/20 ,  H04L49/253 ,  H04L43/028 ,  H04L49/60

CPC分类号： H04L43/10 ,  H04L41/12 ,  H04L43/062 ,  H04L49/3063 ,  H04L69/22

摘要： Network appliances can use packet processing pipeline circuits to implement network rules for processing network packet flows by configuring the pipeline's processing stages to execute specific policies for specific network packets in accordance with the network rules. Trace reports that indicate network rules implemented at specific processing stages can be more informative than those indicating policies implemented by the processing stages. A method implemented by a network appliance can store network rules for processing network flows by the processing stages of a packet processing pipeline circuit. The method can produce a trace report in response to receiving a trace directive for one of the network flows wherein one of the processing stages has applied a network rule to a network packet in one of the network flows. The trace report can indicate the network rule in association with the processing stage and the network flow.

公开(公告)号：US11743123B2

公开(公告)日：2023-08-29

申请号：US16902251

申请日：2020-06-15

申请人： Nicira, Inc.

发明人： Martin Casado ,  Teemu Koponen ,  Pankaj Thakkar

IPC分类号： H04L12/24 ,  H04L12/26 ,  H04L12/46 ,  H04L12/54 ,  H04L12/713 ,  H04L12/911 ,  H04L12/931 ,  H04L12/933 ,  H04L12/935 ,  G06F9/38 ,  G06F11/07 ,  G06F15/16 ,  G06F15/173 ,  H04L41/0893 ,  H04L49/1546 ,  H04L45/586 ,  H04L49/00 ,  H04L47/783 ,  H04L45/00 ,  H04L41/0896 ,  H04L61/5007 ,  H04L45/02 ,  H04L41/0816 ,  H04L41/0853 ,  H04L101/622

CPC分类号： H04L41/0893 ,  G06F15/17312 ,  H04L12/4633 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L45/00 ,  H04L45/02 ,  H04L45/586 ,  H04L47/783 ,  H04L49/00 ,  H04L49/1546 ,  H04L49/3063 ,  H04L49/70 ,  H04L61/5007 ,  G06F11/07 ,  H04L2101/622

摘要： Some embodiments of the invention provide a a method of processing packets associated with a logical switching element implemented by multiple physical switching elements executing on multiple host computers on which multiple machines execute. At a first physical switching element of a first host computer, the method receives a packet from a first machine associated with the logical switching element. For the packet, the method identifies a logical ingress port of the logical switch that is associated with the packet. For the packet, the method also uses the logical ingress port to identify a logical egress port of the logical switch that is associated with the packet. For the packet, the method also uses the logical egress port to identify a physical egress port of the first host computer to use to send the packet along to a second machine associated with the logical egress port. From the identified physical egress port, the method forwards the packet with an encapsulating header that stores the logical egress port.

公开(公告)号：US20230247054A1

公开(公告)日：2023-08-03

申请号：US17587739

申请日：2022-01-28

申请人： Avago Technologies International Sales Pte. Limited

发明人： Rajan Sharma ,  Mark Birman ,  Laxminarasimha Rao Kesiraju

IPC分类号： H04L9/40 ,  H04L49/1546

CPC分类号： H04L63/20 ,  H04L49/1546

摘要： In some aspects, the disclosure is directed to methods and systems for providing an architecture for building high performance silicon components that support a rich set of networking and security features. In many implementations, the architecture splits network and security functions into two functional and logical blocks (which may physically be on the same die or integrated circuit in some implementations, or may be split on separate integrated circuits). The network functions may be executed via an integrated network interface card and accelerator subsystem with a high throughput execution pipeline. Security functions may be executed asynchronously from the network processing functions, in many implementations.