公开(公告)号：US20200226066A1

公开(公告)日：2020-07-16

申请号：US16833337

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Zeshan A. CHISHTI ,  Sanjay K. KUMAR ,  Zvika GREENFIELD ,  Philip LANTZ ,  Eshel SERLIN ,  Asaf RUBINSTEIN ,  Robert J. ROYER, JR.

IPC: G06F12/0811 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/02 ,  G06F11/30 ,  G06F1/30

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.