公开(公告)号：US20190042131A1

公开(公告)日：2019-02-07

申请号：US15940499

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Christopher E. COX ,  Navneet DOUR ,  Asaf RUBINSTEIN ,  Israel DIAMAND

IPC: G06F3/06 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/42

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

公开(公告)号：US20200226066A1

公开(公告)日：2020-07-16

申请号：US16833337

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Eran SHIFER ,  Zeshan A. CHISHTI ,  Sanjay K. KUMAR ,  Zvika GREENFIELD ,  Philip LANTZ ,  Eshel SERLIN ,  Asaf RUBINSTEIN ,  Robert J. ROYER, JR.

IPC: G06F12/0811 ,  G06F12/0882 ,  G06F12/1027 ,  G06F12/02 ,  G06F11/30 ,  G06F1/30

Abstract: An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory having a near memory and a far memory. The memory controller to maintain first and second caches. The first cache to cache pages recently accessed from the far memory. The second cache to cache addresses of pages recently accessed from the far memory. The second cache having a first level and a second level. The first level to cache addresses of pages that are more recently accessed than pages whose respective addresses are cached in the second level. The memory controller comprising logic circuitry to inform system software that: a) a first page in the first cache that is accessed less than other pages in the first cache is a candidate for migration from the far memory to the near memory; and/or, b) a second page whose address travels a threshold number of round trips between the first and second levels of the second cache is a candidate for migration from the far memory to the near memory.

公开(公告)号：US20180189192A1

公开(公告)日：2018-07-05

申请号：US15394550

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Israel DIAMAND ,  Zvika GREENFIELD ,  Julius MANDELBLAT ,  Asaf RUBINSTEIN

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/0864 ,  G06F12/0893

CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/507 ,  G06F2212/608

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

公开(公告)号：US20190108138A1

公开(公告)日：2019-04-11

申请号：US16105434

申请日：2018-08-20

Applicant: Intel Corporation

Inventor： Daniel GREENSPAN ,  Blaise FANNING ,  Yoav LOSSIN ,  Asaf RUBINSTEIN

IPC: G06F12/123 ,  G06F12/0891 ,  G06F12/0897

Abstract: A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy.