公开(公告)号：US20160020897A1

公开(公告)日：2016-01-21

申请号：US14334071

申请日：2014-07-17

Applicant: Intel Corporation

Inventor： TSVIKA KURTS ,  BEEMAN C. STRONG ,  OFER LEVY ,  GABI MALKA ,  ZEEV SPERBER

IPC: H04L7/00

CPC classification number: H04L43/50 ,  H04J3/0664 ,  H04L43/106

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

Abstract translation: 根据本文公开的实施例，提供了用于在跟踪系统（TS）中门限定时分组生成的门限的系统和方法。 例如，该方法可以包括生成并将跟踪数据（TD）分组输出到分组日志中。 该方法还包括当从先前的TM分组的输出超过时钟阈值开始经过了多个时钟周期时，生成并输出与TD分组相对应的定时分组（TM）到分组日志中。