公开(公告)号：US20170262290A1

公开(公告)日：2017-09-14

申请号：US15438679

申请日：2017-02-21

Applicant: Intel Corporation

Inventor： AHMAD YASIN ,  PEGGY J. IRELAN ,  OFER LEVY ,  EMILE ZIEDAN ,  GRANT G. ZHOU

IPC: G06F9/38 ,  G06F11/34

CPC classification number: G06F9/3861 ,  G06F9/3857 ,  G06F11/3466 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/88

Abstract: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

公开(公告)号：US20160020897A1

公开(公告)日：2016-01-21

申请号：US14334071

申请日：2014-07-17

Applicant: Intel Corporation

Inventor： TSVIKA KURTS ,  BEEMAN C. STRONG ,  OFER LEVY ,  GABI MALKA ,  ZEEV SPERBER

IPC: H04L7/00

CPC classification number: H04L43/50 ,  H04J3/0664 ,  H04L43/106

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

Abstract translation: 根据本文公开的实施例，提供了用于在跟踪系统（TS）中门限定时分组生成的门限的系统和方法。 例如，该方法可以包括生成并将跟踪数据（TD）分组输出到分组日志中。 该方法还包括当从先前的TM分组的输出超过时钟阈值开始经过了多个时钟周期时，生成并输出与TD分组相对应的定时分组（TM）到分组日志中。

公开(公告)号：US20170351641A1

公开(公告)日：2017-12-07

申请号：US15490743

申请日：2017-04-18

Applicant: Intel Corporation

Inventor： ZEEV SPERBER ,  ROBERT VALENTINE ,  SHLOMO RAIKIN ,  STANISLAV SHWARTSMAN ,  GAL OFIR ,  IGOR YANOVER ,  GUY PATKIN ,  OFER LEVY

IPC: G06F15/78 ,  G06F9/345 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F15/7839 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3808 ,  G06F9/383

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.