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    TRACKING DEFERRED DATA PACKETS IN A DEBUG TRACE ARCHITECTURE
    2.
    发明申请
    TRACKING DEFERRED DATA PACKETS IN A DEBUG TRACE ARCHITECTURE 有权
    在调试跟踪架构中跟踪预留数据包

    公开(公告)号：US20160170820A1

    公开(公告)日：2016-06-16

    申请号：US14566374

    申请日：2014-12-10

    Applicant: Intel Corporation

    Inventor： BEEMAN C. STRONG ,  STEPHEN J. ROBINSON ,  JASON W. BRANDT ,  PETER LACHNER

    IPC: G06F11/07 ,  G06F11/34

    CPC classification number: G06F11/3466 ,  G06F9/30 ,  G06F11/3636

    Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.

    Abstract translation: 公开了一种在调试跟踪架构中实现跟踪延迟数据分组的处理设备。 处理装置是确定与执行指令相对应的顺序相对于执行指令序列中的指令类型的其他执行指令的顺序，识别对应于第一分组类型的第一数据分组，并依次 根据订单编号对数据跟踪日志中的第一分组类型的数据分组进行排序，识别与第二分组类型对应的第二数据分组，并根据订单号对数据分组进行顺序排序 的数据跟踪日志中的第二分组类型，并将所识别的第一和第二数据分组映射到指令，其中在指令的退休之后生成第一或第二数据分组中的至少一个。

    USING THRESHOLDS TO GATE TIMING PACKET GENERATION IN A TRACING SYSTEM
    3.
    发明申请
    USING THRESHOLDS TO GATE TIMING PACKET GENERATION IN A TRACING SYSTEM 有权
    使用阈值来选择跟踪系统中的时序分组生成

    公开(公告)号：US20160020897A1

    公开(公告)日：2016-01-21

    申请号：US14334071

    申请日：2014-07-17

    Applicant: Intel Corporation

    Inventor： TSVIKA KURTS ,  BEEMAN C. STRONG ,  OFER LEVY ,  GABI MALKA ,  ZEEV SPERBER

    IPC: H04L7/00

    CPC classification number: H04L43/50 ,  H04J3/0664 ,  H04L43/106

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

    Abstract translation: 根据本文公开的实施例，提供了用于在跟踪系统（TS）中门限定时分组生成的门限的系统和方法。 例如，该方法可以包括生成并将跟踪数据（TD）分组输出到分组日志中。 该方法还包括当从先前的TM分组的输出超过时钟阈值开始经过了多个时钟周期时，生成并输出与TD分组相对应的定时分组（TM）到分组日志中。

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