公开(公告)号：US20210326284A1

公开(公告)日：2021-10-21

申请号：US17359027

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Ilya K. Ganusov

IPC: G06F13/28

Abstract: Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).

公开(公告)号：US12197360B2

公开(公告)日：2025-01-14

申请号：US17359027

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Ilya K. Ganusov

IPC: G06F13/28

Abstract: Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).