公开(公告)号：US11749368B2

公开(公告)日：2023-09-05

申请号：US16729085

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Dana How

IPC: G11C29/12 ,  G11C29/56 ,  G11C29/00 ,  G11C29/14 ,  G06F15/78

CPC classification number: G11C29/12015 ,  G06F15/7807 ,  G11C29/14 ,  G11C29/56008 ,  G11C29/789 ,  G11C2029/1206

Abstract: An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path.

公开(公告)号：US20210326284A1

公开(公告)日：2021-10-21

申请号：US17359027

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Ilya K. Ganusov

IPC: G06F13/28

Abstract: Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).

公开(公告)号：US12086460B2

公开(公告)日：2024-09-10

申请号：US17132672

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Jun Pin Tan ,  Yi Peng

IPC: G06F3/06 ,  G06F1/06 ,  G06F30/343

CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0616 ,  G06F3/0673 ,  G06F30/343

Abstract: Systems and methods for non-destructive readback and writeback of an integrated circuit system are provided. Such a system may include an adaptive logic element including a first register pair. The first register pair may include a first register operating at a first frequency and a second register operating at a second frequency. The second frequency may be equal to or lower than the first frequency. The second register may store data from the first register. The adaptive logic element may also include a first clock providing a first clock signal to the first register and a second clock providing a second clock signal. The adaptive logic element may also include a multiplexer that may select the first clock signal or the second clock signal as a clock source for the second register.

公开(公告)号：US12197360B2

公开(公告)日：2025-01-14

申请号：US17359027

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Gaik Ming Chan ,  Ilya K. Ganusov

IPC: G06F13/28

Abstract: Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).

公开(公告)号：US20220187370A1

公开(公告)日：2022-06-16

申请号：US17687064

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Bee Yee Ng ,  Ilya Ganusov

IPC: G01R31/3185 ,  G01R31/317

Abstract: An integrated circuit includes first and second data storage circuits, first, second, and third shadow storage circuits, and first, second, and third multiplexer circuits. The first multiplexer circuit is configurable to provide a state of a data signal from the first data storage circuit to the first shadow storage circuit in a snapshot mode. The second multiplexer circuit is coupled between an output of the second data storage circuit and an input of the second shadow storage circuit. The third multiplexer circuit is coupled to the second multiplexer circuit. The third multiplexer circuit is configurable to provide a state of an output signal of the first shadow storage circuit to an input of the third shadow storage circuit in a scan mode bypassing the second shadow storage circuit.