公开(公告)号：US20210286626A1

公开(公告)日：2021-09-16

申请号：US17213453

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

公开(公告)号：US11748130B2

公开(公告)日：2023-09-05

申请号：US16456300

申请日：2019-06-28

Applicant: INTEL CORPORATION

Inventor： Rajesh Sankaran ,  Bret Toll ,  William Rash ,  Subramaniam Maiyuran ,  Gang Chen ,  Varghese George

IPC: G06F9/455 ,  G06F12/1009 ,  G06T1/20

CPC classification number: G06F9/45558 ,  G06F12/1009 ,  G06T1/20 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2009/45591

Abstract: Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing engines, a memory, a memory management unit (MMU) including a GPU second level page table and GPU dirty bit tracking, and a provisioning agent to receive a request from a virtual machine monitor (VMM) to provision a subcluster of graphics processing apparatuses, the subcluster including a plurality of graphics processing engines from a plurality of graphics processing apparatuses connected using a scale-up fabric, provision the scale-up fabric to route data within the subcluster of graphics processing apparatuses, and provision a plurality of resources on the graphics processing apparatus for the subcluster based on the request from the VMM.

公开(公告)号：US11537403B2

公开(公告)日：2022-12-27

申请号：US17213453

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/20

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

公开(公告)号：US12229581B2

公开(公告)日：2025-02-18

申请号：US18239489

申请日：2023-08-29

Applicant: INTEL CORPORATION

Inventor： Rajesh Sankaran ,  Bret Toll ,  William Rash ,  Subramaniam Maiyuran ,  Gang Chen ,  Varghese George

IPC: G06F9/455 ,  G06F12/1009 ,  G06T1/20

Abstract: Graphics processing systems and methods are described. A graphics processing apparatus may comprise one or more graphics processing engines, a memory, a memory management unit (MMU) including a GPU second level page table and GPU dirty bit tracking, and a provisioning agent to receive a request from a virtual machine monitor (VMM) to provision a subcluster of graphics processing apparatuses, the subcluster including a plurality of graphics processing engines from a plurality of graphics processing apparatuses connected using a scale-up fabric, provision the scale-up fabric to route data within the subcluster of graphics processing apparatuses, and provision a plurality of resources on the graphics processing apparatus for the subcluster based on the request from the VMM.

公开(公告)号：US10990409B2

公开(公告)日：2021-04-27

申请号：US15493442

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/20

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

公开(公告)号：US20180121202A1

公开(公告)日：2018-05-03

申请号：US15341273

申请日：2016-11-02

Applicant: Intel Corporation

Inventor： Gang Chen ,  Pratik J. Ashar ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3887

Abstract: Methods and apparatus relating to techniques for improved SIMD channel utilization in a divergent control flow environment. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine instructions in an instruction set which are combinable into a super-instruction to execute in a divergent control flow environment, combine a first instruction and a second instruction to form a super-instruction, encode the super-instruction, and queue the super-instruction for execution on a processor. Other embodiments are also disclosed and claimed.