公开(公告)号：US20210091194A1

公开(公告)日：2021-03-25

申请号：US16579069

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Richard VREELAND ,  Giselle ELBAZ ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Gurpreet SINGH ,  Florian GSTREIN ,  Nafees KABIR ,  Tristan A. TRONIC ,  Eungnak HAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US20240047543A1

公开(公告)日：2024-02-08

申请号：US18382339

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Richard VREELAND ,  Giselle ELBAZ ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Gurpreet SINGH ,  Florian GSTREIN ,  Nafees KABIR ,  Tristan A. TRONIC ,  Eungnak HAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L29/7851 ,  H01L23/5226 ,  H01L29/41775 ,  H01L27/0886 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823468 ,  H01L21/823431

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.