公开(公告)号：US09595531B2

公开(公告)日：2017-03-14

申请号：US14329644

申请日：2014-07-11

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Gordon A Haller ,  Fatma A Simsek-Ege

IPC: H01L29/80 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11558

Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.

Abstract translation: 具有氧化铝（AlOx）层作为贵金属HiK层的多层堆叠的存储单元以提供蚀刻停止选择性。 堆叠的每层包括存储单元设备。 该电路包括与存储器单元的多层堆叠相邻的源极选择多晶（SGS多晶）层，其中SGS多晶硅层为多层堆叠的存储单元提供栅极选择信号。 该电路还包括导电源层，以为层叠层的通道提供源极导体。 AlOx层设置在源层和SGS多晶硅层之间，并提供干蚀刻选择性和湿蚀刻选择性，以创建用于将存储单元电耦合到源层的通道。