公开(公告)号：US10134758B2

公开(公告)日：2018-11-20

申请号：US15683672

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/768 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US20180096955A1

公开(公告)日：2018-04-05

申请号：US15283327

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Minsoo Lee ,  Gordon A. Haller ,  Philip J. Ireland

IPC: H01L23/58 ,  H01L23/00 ,  H01L21/3065 ,  H01L21/3205

CPC classification number: H01L23/585 ,  H01L21/3065 ,  H01L21/32051 ,  H01L23/53271 ,  H01L23/562 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/3512

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

公开(公告)号：US10707121B2

公开(公告)日：2020-07-07

申请号：US15396469

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Jun Liu ,  Mark A. Levan ,  Gordon A. Haller ,  Fei Wang ,  Wei Yeeng Ng ,  Wesley O. McKinsey ,  Zhiqiang Xie ,  Jeremy F. Adams ,  Hongbin Zhu ,  Jun Zhao

IPC: H01L21/768 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11526 ,  H01L27/11548 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: Conductive structure technology is disclosed. In one example, a conductive structure can include an interconnect and a plurality of conductive layers overlying the interconnect. Each conductive layer can be separated from an adjacent conductive layer by an insulative layer. In addition, the conductive structure can include a contact extending through the plurality of conductive layers to the interconnect. The contact can be electrically coupled to the interconnect and insulated from the plurality of conductive layers. Associated systems and methods are also disclosed.

公开(公告)号：US10453829B2

公开(公告)日：2019-10-22

申请号：US15625350

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Merri Lyn Carlson ,  Hongbin Zhu ,  Gordon A. Haller ,  James E. Davis ,  Kevin G. Duesman ,  James Mathew ,  Michael P. Violette

IPC: H01L27/11556 ,  H01L25/10 ,  H01L27/11529 ,  H01L27/11548

Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.

公开(公告)号：US20180130819A1

公开(公告)日：2018-05-10

申请号：US15683672

申请日：2017-08-22

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L21/768 ,  G11C16/24

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US09741734B2

公开(公告)日：2017-08-22

申请号：US14970288

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Jun Zhao ,  Purnima Narayanan ,  Gordon Haller ,  Damir Fazil

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/1157

Abstract: 3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.

公开(公告)号：US10002767B2

公开(公告)日：2018-06-19

申请号：US15418618

申请日：2017-01-27

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Gordon A. Haller ,  Fatma A. Simsek-Ege

IPC: H01L27/115 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11558

Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.

公开(公告)号：US09595531B2

公开(公告)日：2017-03-14

申请号：US14329644

申请日：2014-07-11

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Gordon A Haller ,  Fatma A Simsek-Ege

IPC: H01L29/80 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11558

Abstract: A multitier stack of memory cells having an aluminum oxide (AlOx) layer as a noble HiK layer to provide etch stop selectivity. Each tier of the stack includes a memory cell device. The circuit includes a source gate select polycrystalline (SGS poly) layer adjacent the multitier stack of memory cells, wherein the SGS poly layer is to provide a gate select signal for the memory cells of the multitier stack. The circuit also includes a conductive source layer to provide a source conductor for a channel for the tiers of the stack. The AlOx layer is disposed between the source layer and the SGS poly layer and provides both dry etch selectivity and wet etch selectivity for creating a channel to electrically couple the memory cells to the source layer.

Abstract translation: 具有氧化铝（AlOx）层作为贵金属HiK层的多层堆叠的存储单元以提供蚀刻停止选择性。 堆叠的每层包括存储单元设备。 该电路包括与存储器单元的多层堆叠相邻的源极选择多晶（SGS多晶）层，其中SGS多晶硅层为多层堆叠的存储单元提供栅极选择信号。 该电路还包括导电源层，以为层叠层的通道提供源极导体。 AlOx层设置在源层和SGS多晶硅层之间，并提供干蚀刻选择性和湿蚀刻选择性，以创建用于将存储单元电耦合到源层的通道。

公开(公告)号：US11018097B2

公开(公告)日：2021-05-25

申请号：US16707188

申请日：2019-12-09

Applicant: Intel Corporation

Inventor： Hongbin Zhu ,  Minsoo Lee ,  Gordon A. Haller ,  Philip J. Ireland

IPC: H01L23/58 ,  H01L23/532 ,  H01L21/3065 ,  H01L21/3205 ,  H01L23/00

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

公开(公告)号：US20180366453A1

公开(公告)日：2018-12-20

申请号：US15625350

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Merri Lyn Carlson ,  Hongbin Zhu ,  Gordon A. Haller ,  James E. Davis ,  Kevin G. Duesman ,  James Mathew ,  Michael P. Violette

IPC: H01L25/10 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L25/105 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556

Abstract: In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.