公开(公告)号：US20190237466A1

公开(公告)日：2019-08-01

申请号：US16318361

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Patrick H. KEYS ,  Hei KAM ,  Rishabh MEHANDRU ,  Aaron A. BUDREVICH

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/167 ,  H01L29/43 ,  H01L29/49 ,  H01L29/66795 ,  H01L29/785

Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.

公开(公告)号：US20190019891A1

公开(公告)日：2019-01-17

申请号：US16070262

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN ,  Chandra S. MOHAPATRA ,  Hei KAM ,  Nabil G. MISTKAWI ,  Jun Sung KANG ,  Biswajeet GUHA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/423

Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.