公开(公告)号：US20190148378A1

公开(公告)日：2019-05-16

申请号：US16242946

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Anand S. MURTHY ,  Tahir GHANI ,  Willy RACHMADY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Glenn A. GLASS

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/205 ,  H01L29/423 ,  H01L21/8258 ,  H01L29/10

Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.

公开(公告)号：US20180158927A1

公开(公告)日：2018-06-07

申请号：US15575810

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Glenn A. GLASS ,  Willy RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Matthew V. METZ

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66522 ,  B82Y10/00 ,  H01L21/02395 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30612 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.

公开(公告)号：US20210296180A1

公开(公告)日：2021-09-23

申请号：US17336565

申请日：2021-06-02

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Willy RACHMADY ,  Anand S. MURTHY ,  Chandra S. MOHAPATRA ,  Tahir GHANI ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC: H01L21/8234 ,  H01L21/02

Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfin structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.

公开(公告)号：US20190035897A1

公开(公告)日：2019-01-31

申请号：US16072313

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Harold W. KENNEL ,  Glenn A. GLASS ,  Will RACHMADY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI ,  Matthew V. METZ ,  Sean T. MA

IPC: H01L29/205 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/205 ,  H01L27/0924 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.

公开(公告)号：US20190035926A1

公开(公告)日：2019-01-31

申请号：US16070207

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN

IPC: H01L29/78 ,  H01L21/764 ,  H01L29/66 ,  H01L29/10

Abstract: A replacement fin layer is deposited on a sub-fin layer in trenches isolated by an insulating layer on a substrate. The replacement fin layer has first component rich side portions and a second component rich core portion. The second component rich core portion is etched to generate a double fin structure comprising the first component rich fins.

公开(公告)号：US20190019891A1

公开(公告)日：2019-01-17

申请号：US16070262

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Glenn A. GLASS ,  Anand S. MURTHY ,  Karthik JAMBUNATHAN ,  Chandra S. MOHAPATRA ,  Hei KAM ,  Nabil G. MISTKAWI ,  Jun Sung KANG ,  Biswajeet GUHA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/423

Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.

公开(公告)号：US20180315827A1

公开(公告)日：2018-11-01

申请号：US15770468

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sean T. MA ,  Willy RACHMADY ,  Matthew V. METZ ,  Chandra S. MOHAPATRA ,  Gilbert DEWEY ,  Nadia M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  Anand S. MURTHY

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28264 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

公开(公告)号：US20170263706A1

公开(公告)日：2017-09-14

申请号：US15529481

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia M. RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0673 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

公开(公告)号：US20200066855A1

公开(公告)日：2020-02-27

申请号：US16074373

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. MOHAPATRA ,  Glenn A. GLASS ,  Harold W. KENNEL ,  Anand S. MURTHY ,  Willy RACHMADY ,  Gilbert DEWEY ,  Sean T. MA ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Tahir GHANI

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/201

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

公开(公告)号：US20190341481A1

公开(公告)日：2019-11-07

申请号：US16309049

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Willy RACHMADY ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Sean T. MA ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: An apparatus is described. The apparatus includes a FINFET transistor. The FINFET transistor comprises a tapered subfin structure having a sidewall surface area that is large enough to induce aspect ratio trapping of lattice defects along sidewalls of the subfin structure so that the defects are substantially prevented from reaching said FINFET transistor's channel.