公开(公告)号：US20180189238A1

公开(公告)日：2018-07-05

申请号：US15395786

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Horace Lau ,  Tony L. Werner

IPC: G06F17/16

CPC classification number: G06F17/16 ,  G06N3/0454 ,  G06N3/084

Abstract: In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the max pooling operation using the one or more matrix operands; and obtain a result of the max pooling operation.

公开(公告)号：US10896039B2

公开(公告)日：2021-01-19

申请号：US16264483

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Tony L. Werner ,  Aravind Kalaiah ,  Vijay Korthikanti ,  Horace Lau

IPC: G06F9/30 ,  G06N3/063 ,  G06N3/08

Abstract: In one embodiment, a matrix operation may be performed on one or more matrix operands. For example, matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands. The one or more matrix operands may be extracted from the matrix data. A matrix routine associated with the matrix operation may be identified. The matrix routine may be executed on a matrix processor using the one or more matrix operands. A result of the matrix operation may be obtained based on the matrix routine executed by the matrix processor.

公开(公告)号：US20180188972A1

公开(公告)日：2018-07-05

申请号：US15395427

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Andrew Yang ,  Carey K. Kloss ,  Tony L. Werner ,  Horace Lau

IPC: G06F3/06 ,  G06F17/16

CPC classification number: G06F3/0611 ,  G06F3/0646 ,  G06F3/0658 ,  G06F3/0673 ,  G06F11/1048 ,  G06F17/16 ,  G11C7/10 ,  G11C7/1006

Abstract: In one embodiment, an apparatus comprises a memory and a memory controller. The memory comprises a plurality of memory modules, wherein each memory module comprises a plurality of storage locations. The memory controller may be configured to write data of a matrix to the memory. For example, the memory controller may be configured to write a particular row or a particular column of the matrix to the memory by: shifting a plurality of matrix elements of the particular row or the particular column; and writing the plurality of matrix elements to the plurality of memory modules.

公开(公告)号：US20170097884A1

公开(公告)日：2017-04-06

申请号：US14874784

申请日：2015-10-05

Applicant: Intel Corporation

Inventor： Tony Werner ,  Aravind Kalaiah ,  Andrew Yang ,  Carey Kloss ,  Horace Lau ,  Naveen Gandham Rao ,  Amir Khosrowshahi

IPC: G06F12/02 ,  G06F9/30

CPC classification number: G06F12/023 ,  G06F15/76 ,  G06F2212/251 ,  G06T1/20

Abstract: Described herein are one or more integrated circuits (ICs) comprising controller circuitry to receive a command to execute an operation for data inputs stored in an external memory or a local memory, and convert the operation into a set of matrix operations to operate on sub-portions of the data inputs. The IC(s) further comprise at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include ALUs, a local memory external to the ALUs and accessible by the ALUs, and processing control circuitry to create at least one matrix operand in the local memory (from the data inputs of the operation) comprising at least one of a scalar, a vector, or a 2D matrix, and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing a matrix operation.

公开(公告)号：US10228937B2

公开(公告)日：2019-03-12

申请号：US15395654

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Tony L. Werner ,  Aravind Kalaiah ,  Vijay Korthikanti ,  Horace Lau

IPC: G06F9/30

Abstract: An apparatus may comprise a multi-dimensional memory, a plurality of matrix processors, and a matrix routine memory. The matrix routine memory may store a plurality of programmable matrix routines, wherein each programmable matrix routine comprises a plurality of instructions associated with a particular matrix operation, wherein the plurality of instructions is to be executed by the plurality of matrix processors. Further, the plurality of matrix processors may be configured to: receive a command to perform a matrix operation; receive matrix data from the multi-dimensional memory; extract one or more matrix operands from the matrix data; identify a programmable matrix routine associated with the matrix operation; receive the programmable matrix routine from the matrix routine memory; execute the programmable matrix routine using the one or more matrix operands; and obtain a result of the matrix operation based on execution of the programmable matrix routine.

公开(公告)号：US09886377B2

公开(公告)日：2018-02-06

申请号：US14874784

申请日：2015-10-05

Applicant: Intel Corporation

Inventor： Tony Werner ,  Aravind Kalaiah ,  Andrew Yang ,  Carey Kloss ,  Horace Lau ,  Naveen Gandham Rao ,  Amir Khosrowshahi

IPC: G06F12/00 ,  G06F12/02 ,  G06F15/76 ,  G06T1/20

CPC classification number: G06F12/023 ,  G06F15/76 ,  G06F2212/251 ,  G06T1/20

Abstract: Described herein are one or more integrated circuits (ICs) comprising controller circuitry to receive a command to execute an operation for data inputs stored in an external memory or a local memory, and convert the operation into a set of matrix operations to operate on sub-portions of the data inputs. The IC(s) further comprise at least one processing circuitry to execute the set of matrix operations, the processing circuitry to include ALUs, a local memory external to the ALUs and accessible by the ALUs, and processing control circuitry to create at least one matrix operand in the local memory (from the data inputs of the operation) comprising at least one of a scalar, a vector, or a 2D matrix, and provide memory handles corresponding to each of the matrix operands to one of the ALUs to access the respective matrix operands when executing a matrix operation.

公开(公告)号：US20190171690A1

公开(公告)日：2019-06-06

申请号：US16266847

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Horace Lau ,  Tony L. Werner

IPC: G06F17/16 ,  G06N3/08 ,  G06N3/04

Abstract: In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the max pooling operation using the one or more matrix operands; and obtain a result of the max pooling operation.

公开(公告)号：US20190171450A1

公开(公告)日：2019-06-06

申请号：US16264483

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Tony L. Werner ,  Aravind Kalaiah ,  Vijay Korthikanti ,  Horace Lau

IPC: G06F9/30 ,  G06N3/08 ,  G06N3/063

Abstract: In one embodiment, a matrix operation may be performed on one or more matrix operands. For example, matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands. The one or more matrix operands may be extracted from the matrix data. A matrix routine associated with the matrix operation may be identified. The matrix routine may be executed on a matrix processor using the one or more matrix operands. A result of the matrix operation may be obtained based on the matrix routine executed by the matrix processor.

公开(公告)号：US10198401B2

公开(公告)日：2019-02-05

申请号：US15395786

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Horace Lau ,  Tony L. Werner

IPC: G06F17/16 ,  G06N3/08

Abstract: In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the max pooling operation using the one or more matrix operands; and obtain a result of the max pooling operation.

公开(公告)号：US20180189057A1

公开(公告)日：2018-07-05

申请号：US15395654

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Tony L. Werner ,  Aravind Kalaiah ,  Vijay Korthikanti ,  Horace Lau

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30043

Abstract: In one embodiment, a matrix operation may be performed on one or more matrix operands. For example, matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands. The one or more matrix operands may be extracted from the matrix data. A matrix routine associated with the matrix operation may be identified. The matrix routine may be executed on a matrix processor using the one or more matrix operands. A result of the matrix operation may be obtained based on the matrix routine executed by the matrix processor.